X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fpipeline_tb.vhd;h=47406cab3f02f6b55dbf13bee70f23c3c9ab26a3;hb=61ccae8df4f138fd753bd1e5e7e8b8f25159d969;hp=ff8fd608d31130bcc5c5301772251fbcb39c9651;hpb=a0d00315e885eff5fb171ad47de60106435a7a2b;p=calu.git diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd index ff8fd60..47406ca 100644 --- a/cpu/src/pipeline_tb.vhd +++ b/cpu/src/pipeline_tb.vhd @@ -18,8 +18,10 @@ end pipeline_tb; ------------------------------------------------------------------------------- architecture behavior of pipeline_tb is - constant cc : time := 30 ns; -- test clock period - + constant cc : time := 20 ns; -- test clock period + constant SYS_CLOCK_FREQ : integer := 50000000; + constant BAUD_COUNT : integer := SYS_CLOCK_FREQ/115200; + signal sys_clk_pin : std_logic; signal sys_res_n_pin : std_logic; --Data input @@ -31,6 +33,7 @@ architecture behavior of pipeline_tb is signal branch_prediction_bit_pin : std_logic; signal alu_jump_bit_pin : std_logic; signal instruction_pin : instruction_word_t; + signal prog_cnt : instruction_addr_t; signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0); signal reg_wr_data_pin : gp_register_t; @@ -47,14 +50,19 @@ architecture behavior of pipeline_tb is signal dmem_pin : std_logic;--memop signal dmem_wr_en_pin : std_logic; signal hword_pin : std_logic; - signal byte_s_pin : std_logic; + signal byte_s_pin, tx_pin, rx_pin : std_logic; + + signal gpm_in_pin : extmod_rec; + signal gpm_out_pin : gp_register_t; signal nop_pin : std_logic; - -- extension signals - signal ext_gpmp : extmod_rec; - signal pointer : pointer_count; - signal dec_in,p_en : std_logic; - signal data_out : gp_register_t; - signal pointer_val : gp_register_t; + + signal cycle_cnt : integer; + + signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6); + signal int_req_pin : interrupt_t; + + signal new_im_data :std_logic; + signal im_addr, im_data : gp_register_t; begin @@ -90,10 +98,15 @@ begin prediction_result => prediction_result_pin, --: in instruction_addr_t; branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic; alu_jump_bit => alu_jump_bit_pin, --: in std_logic; + new_im_data_in => new_im_data, + im_addr => im_addr, + im_data => im_data, --Data outputs - instruction => instruction_pin --: out instruction_word_t - ); + instruction => instruction_pin, --: out instruction_word_t + prog_cnt => prog_cnt, + int_req => int_req_pin + ); decode_st : decode_stage generic map ( @@ -110,6 +123,7 @@ begin --Data inputs instruction => instruction_pin, --: in instruction_word_t; + prog_cnt => prog_cnt, reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0); reg_wr_data => reg_wr_data_pin, --: in gp_register_t; reg_we => reg_we_pin, --: in std_logic; @@ -123,33 +137,19 @@ begin ); exec_st : execute_stage generic map('0') - port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin, - data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin); + port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin, + data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin); writeback_st : writeback_stage - generic map('0', '1') + generic map('0', '1', "altera") port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin, - reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin); - + reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin); - gpmp_inst : extension - generic map ('0') - port map ( - sys_clk_pin, - sys_res_n_pin, - ext_gpmp, - pointer, - dec_in, - p_en, - data_out, - pointer_val - - ); - nop_pin <= (alu_jump_bit_pin xor brpr_pin); + nop_pin <= (alu_jump_bit_pin);-- xor brpr_pin); ------------------------------------------------------------------------------- -- generate simulation clock @@ -162,6 +162,18 @@ begin wait for cc/2; end process CLKGEN; + + cnt : process(sys_clk_pin, sys_res_n_pin) + + begin + + if (sys_res_n_pin = '0') then + cycle_cnt <= 0; + elsif (sys_clk_pin'event and sys_clk_pin = '1') then + cycle_cnt <= cycle_cnt + 1; + end if; + + end process cnt; ------------------------------------------------------------------------------- -- test the design ------------------------------------------------------------------------------- @@ -174,12 +186,26 @@ begin wait until sys_clk_pin = '1' and sys_clk_pin'event; end loop; end; + + procedure txd(trans_data : in std_logic_vector) is + begin + for i in 0 to 9 loop + rx_pin <= trans_data(i); + report "bit: " & std_logic'image(trans_data(i)); + dummy <= not dummy; + wait on dummy; + -- icwait(BAUD_COUNT); + icwait(50); + end loop; + end txd; + begin ----------------------------------------------------------------------------- -- initial reset ----------------------------------------------------------------------------- sys_res_n_pin <= '0'; + rx_pin <= '1'; -- reg_w_addr_pin <= (others => '0'); -- reg_wr_data_pin <= (others => '0'); -- reg_we_pin <= '0'; @@ -189,8 +215,14 @@ begin sys_res_n_pin <= '1'; wait until sys_res_n_pin = '1'; + icwait(10); + + txd("0000100101"); + icwait(600); + icwait(600); - icwait(100000); + txd("0000100101"); + icwait(600000000); --------------------------------------------------------------------------- -- exit testbench