X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fpipeline_tb.vhd;h=47406cab3f02f6b55dbf13bee70f23c3c9ab26a3;hb=61ccae8df4f138fd753bd1e5e7e8b8f25159d969;hp=de276a8fc8f305a9cdb46437ca626d3b1a484eb1;hpb=7c21f901c3a852725bec1e9691627c3280ad6ae0;p=calu.git

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index de276a8..47406ca 100644
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -61,6 +61,9 @@ architecture behavior of pipeline_tb is
 		signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
 		signal int_req_pin : interrupt_t;
 
+		signal new_im_data :std_logic;
+		signal im_addr, im_data : gp_register_t;
+
 begin
 
 --		instruction_ram : r_w_ram
@@ -95,6 +98,9 @@ begin
 			prediction_result => prediction_result_pin, --: in instruction_addr_t;
 			branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
 			alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
+			new_im_data_in => new_im_data,
+			im_addr => im_addr,
+			im_data => im_data,
 
 		--Data outputs
 			instruction => instruction_pin, --: out instruction_word_t
@@ -135,10 +141,10 @@ begin
                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
           writeback_st : writeback_stage
-                generic map('0', '1')
+                generic map('0', '1', "altera")
                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, sseg0, sseg1, sseg2, sseg3, int_req_pin);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin);
 
 
 
@@ -185,9 +191,11 @@ begin
 	begin
 		for i in 0 to 9 loop
 			rx_pin <= trans_data(i);
+			report "bit: " & std_logic'image(trans_data(i));
 			dummy <= not dummy;
 			wait on dummy;
-			icwait(BAUD_COUNT);
+			-- icwait(BAUD_COUNT);
+			icwait(50);
 		end loop;
 	end txd;
 
@@ -197,6 +205,7 @@ begin
     -- initial reset
     -----------------------------------------------------------------------------
 	sys_res_n_pin <= '0';
+	rx_pin <= '1';
 --	reg_w_addr_pin <= (others => '0');
 --	reg_wr_data_pin <= (others => '0');
 --	reg_we_pin <= '0';
@@ -208,9 +217,12 @@ begin
 	
 	icwait(10);
 
-	txd("0100000101");
+	txd("0000100101");
+	icwait(600);
+	icwait(600);
 
-	icwait(1000000000);
+	txd("0000100101");
+	icwait(600000000);
 
     ---------------------------------------------------------------------------
     -- exit testbench