X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fpipeline_tb.vhd;h=47406cab3f02f6b55dbf13bee70f23c3c9ab26a3;hb=61ccae8df4f138fd753bd1e5e7e8b8f25159d969;hp=d87cee18d26c4f271b2cc9e479f89c26840b2d72;hpb=4d230c21bb8c9c23c3dd3349f8736b84987eab0d;p=calu.git

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index d87cee1..47406ca 100644
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -18,8 +18,10 @@ end pipeline_tb;
 -------------------------------------------------------------------------------
 architecture behavior of pipeline_tb is
 
-	constant cc : time := 30 ns;        -- test clock period
-	
+	constant cc : time := 20 ns;        -- test clock period
+	constant SYS_CLOCK_FREQ : integer := 50000000;
+	constant BAUD_COUNT : integer := SYS_CLOCK_FREQ/115200;
+
 		signal sys_clk_pin : std_logic;
 		signal sys_res_n_pin : std_logic;
 		--Data input
@@ -48,7 +50,7 @@ architecture behavior of pipeline_tb is
                  signal dmem_pin  : std_logic;--memop
                  signal dmem_wr_en_pin : std_logic;
                  signal hword_pin  : std_logic;
-                 signal byte_s_pin : std_logic;
+                 signal byte_s_pin, tx_pin, rx_pin : std_logic;
 				 
 				  signal gpm_in_pin : extmod_rec;
 				 signal gpm_out_pin : gp_register_t;
@@ -56,6 +58,11 @@ architecture behavior of pipeline_tb is
 
 		 signal cycle_cnt : integer;
 
+		signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
+		signal int_req_pin : interrupt_t;
+
+		signal new_im_data :std_logic;
+		signal im_addr, im_data : gp_register_t;
 
 begin
 
@@ -91,10 +98,14 @@ begin
 			prediction_result => prediction_result_pin, --: in instruction_addr_t;
 			branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
 			alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
+			new_im_data_in => new_im_data,
+			im_addr => im_addr,
+			im_data => im_data,
 
 		--Data outputs
 			instruction => instruction_pin, --: out instruction_word_t
-			prog_cnt => prog_cnt
+			prog_cnt => prog_cnt,
+			int_req => int_req_pin
 		);	
 
 	decode_st : decode_stage
@@ -130,10 +141,10 @@ begin
                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
           writeback_st : writeback_stage
-                generic map('0', '1')
+                generic map('0', '1', "altera")
                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin);
 
 
 
@@ -175,12 +186,26 @@ begin
         wait until sys_clk_pin = '1' and sys_clk_pin'event;
       end loop;
     end;
+
+	procedure txd(trans_data : in std_logic_vector) is
+	begin
+		for i in 0 to 9 loop
+			rx_pin <= trans_data(i);
+			report "bit: " & std_logic'image(trans_data(i));
+			dummy <= not dummy;
+			wait on dummy;
+			-- icwait(BAUD_COUNT);
+			icwait(50);
+		end loop;
+	end txd;
+
 	
   begin
     -----------------------------------------------------------------------------
     -- initial reset
     -----------------------------------------------------------------------------
 	sys_res_n_pin <= '0';
+	rx_pin <= '1';
 --	reg_w_addr_pin <= (others => '0');
 --	reg_wr_data_pin <= (others => '0');
 --	reg_we_pin <= '0';
@@ -190,8 +215,14 @@ begin
 	sys_res_n_pin <= '1';
 	wait until sys_res_n_pin = '1';
 	
+	icwait(10);
+
+	txd("0000100101");
+	icwait(600);
+	icwait(600);
 
-	icwait(1000000000);
+	txd("0000100101");
+	icwait(600000000);
 
     ---------------------------------------------------------------------------
     -- exit testbench