X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Ffetch_stage_b.vhd;h=59e5d9980c391138743a7e812940af2752cf6c2a;hb=1968f329b10681b760faec9369aa893cd2af8d44;hp=6a6380c838532efc7ec592e85b7a9cf3a79cc7fa;hpb=1a2e51983b5e25fec44b1ef9b1f61f22dce19afa;p=calu.git

diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd
index 6a6380c..59e5d99 100644
--- a/cpu/src/fetch_stage_b.vhd
+++ b/cpu/src/fetch_stage_b.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
@@ -52,20 +73,22 @@ begin
 
 	if (reset = RESET_VALUE) then
 		instr_r_addr <= (others => '0');
-		rom_ram <= ROM_USE;	
+		rom_ram <= ROM_USE;
+		led2 <= '0';
 	elsif rising_edge(clk) then
 		instr_r_addr <= instr_r_addr_nxt;		
 		rom_ram <= rom_ram_nxt;
+		led2 <= rom_ram; --rom_ram_nxt;
 	end if;
 	
 end process; 
 
 
-asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req)
-
+asyn: process(reset, s_reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req)
+variable instr_pc  : instruction_addr_t;
 begin
 	rom_ram_nxt <= rom_ram;
-
+	
 	case rom_ram is
 		when ROM_USE =>
 			instruction <= instr_rd_data_rom;
@@ -74,13 +97,14 @@ begin
 		when others => 
 			instruction <= x"F0000000";
 	end case;
-	instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);
+	instr_pc := std_logic_vector(unsigned(instr_r_addr) + 1);
+	instr_r_addr_nxt <= instr_pc;
 
-	if (instr_r_addr(ROM_INSTR_ADDR_WIDTH) = '1' and rom_ram = ROM_USE) then
+	if (instr_pc = x"0000007f" and rom_ram = ROM_USE) then
 		rom_ram_nxt <= RAM_USE;
 		instr_r_addr_nxt <= (others => '0');
 	end if;
-	
+
 	if (reset = RESET_VALUE) then
 		instr_r_addr_nxt <= (others => '0');
 	end if;
@@ -106,21 +130,24 @@ begin
 		when others => null;
 	end case;
 
+	if (s_reset = RESET_VALUE) then
+		rom_ram_nxt <= RAM_USE;
+		instr_r_addr_nxt <= (others => '0');
+	end if;	
+
 end process;
 
 out_logic : process (instr_r_addr, alu_jump_bit, int_req, jump_result)
 
 begin
-	prog_cnt(10 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
-	prog_cnt(31 downto 11) <= (others => '0');
+	prog_cnt(PHYS_INSTR_ADDR_WIDTH-1 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
+	prog_cnt(INSTR_ADDR_WIDTH-1 downto PHYS_INSTR_ADDR_WIDTH) <= (others => '0');
 
 	if (int_req /= IDLE and alu_jump_bit = LOGIC_ACT ) then
-		prog_cnt(10 downto 0) <= jump_result(10 downto 0);
+		prog_cnt(PHYS_INSTR_ADDR_WIDTH-1 downto 0) <= jump_result(PHYS_INSTR_ADDR_WIDTH-1 downto 0);
 	end if;
 
 end process;
 
-led2 <= rom_ram;
-
 end behav;