X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fextension_uart_pkg.vhd;h=f3eb6aa686fe5fe2bdd320b73567c17dda2af4d9;hb=1968f329b10681b760faec9369aa893cd2af8d44;hp=80df4b27627ac3298b7589e30114246cddd14c4b;hpb=2497f386feef0dca2099fa609d3c1e78db8c5206;p=calu.git

diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd
index 80df4b2..f3eb6aa 100644
--- a/cpu/src/extension_uart_pkg.vhd
+++ b/cpu/src/extension_uart_pkg.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 
 use IEEE.std_logic_1164.all;
@@ -16,19 +37,22 @@ package extension_uart_pkg is
 --RS232
 constant UART_WIDTH : integer := 8;
 subtype uart_data is std_logic_vector(UART_WIDTH-1 downto 0);
-constant BAUD_RATE_WITH : integer := 16;
-subtype baud_rate_l is std_logic_vector(BAUD_RATE_WITH-1 downto 0);
+constant BAUD_RATE_WIDTH : integer := 16;
+subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
 --CLKs
-constant CLK_FREQ_MHZ : real := 33.33;
-constant BAUD_RATE : integer := 115200;
+--constant CLK_FREQ_MHZ : real := 33.33;
+--constant BAUD_RATE : integer := 115200;
 --constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
-constant CLK_PER_BAUD : integer := 16330000;
+-- constant CLK_PER_BAUD : integer := 434;
+-- constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud
+-- constant CLK_PER_BAUD : integer := 50; -- @modelsim
 
  component extension_uart is
         --some modules won't need all inputs/outputs
 	generic	(
 			-- active reset value
-			RESET_VALUE : std_logic
+			RESET_VALUE : std_logic;
+			CLK_PER_BAUD : integer
 			);
 	port(
 		--System inputs
@@ -37,6 +61,8 @@ constant CLK_PER_BAUD : integer := 16330000;
 		-- general extension interface			
 			ext_reg  : in extmod_rec;
 			data_out : out gp_register_t;
+
+			uart_int : out std_logic;
 		-- Input
 			bus_rx : in std_logic;
 		-- Ouput
@@ -70,7 +96,8 @@ end component rs232_tx;
 component rs232_rx is
 	generic	(
 		-- active reset value
-		RESET_VALUE : std_logic
+		RESET_VALUE : std_logic;
+		SYNC_STAGES : integer range 2 to integer'high
 		);
 
 	port(
@@ -79,11 +106,12 @@ component rs232_rx is
 		sys_res_n : in std_logic;
 
 		--Bus
-		bus_rx : in std_logic;
+		bus_rx_unsync : in std_logic;
 
 		--To sendlogic
 		new_rx_data : out std_logic;
-		rx_data : out uart_data
+		rx_data : out uart_data;
+		bd_rate : in baud_rate_l
 	);
 end component rs232_rx;