X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fextension_uart_pkg.vhd;h=a7f14d9442c611e0b4820308107ec3409b31afba;hb=61ccae8df4f138fd753bd1e5e7e8b8f25159d969;hp=fb839ffc5476682aad0baa802667f5bd76996fe4;hpb=78a9fd24aa757de9e088709eae264576ad485158;p=calu.git

diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd
index fb839ff..a7f14d9 100644
--- a/cpu/src/extension_uart_pkg.vhd
+++ b/cpu/src/extension_uart_pkg.vhd
@@ -4,48 +4,27 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
-
+use work.extension_pkg.all;
 
 package extension_uart_pkg is
 
-constant EXTWORDL : integer := log2c(4);
-constant BYTEADDR : integer := log2c(4);
-constant PCOUNT   : integer := 3;
-constant EXTWORDS : integer := EXTWORDL + BYTEADDR;
-
-subtype ext_addrid_t  is std_logic_vector(gp_register_t'high - EXTWORDS downto 0);
-subtype ext_addr_t    is std_logic_vector((gp_register_t'high-BYTEADDR) downto 0);    
-subtype paddr_t is std_logic_vector(log2c(PCOUNT)-1 downto 0);   
-
-        type extmod_rec is record
-                sel   : std_logic;
-                wr_en : std_logic;
-                byte_en : std_logic_vector(gp_register_t'length/byte_t'length-1 downto 0); 
-                data : gp_register_t;
-                addr : ext_addr_t;     
-        end record; 
-
-
-type status_rec is record
-		zero : std_logic;
-		oflo : std_logic;
-		sign : std_logic;
-		carry : std_logic;
-end record;
-
-constant EXT_7SEG_ADDR:   ext_addrid_t := x"FFFFFFA";
-constant EXT_EXTMEM_ADDR: ext_addrid_t := x"FFFFFFB";
-constant EXT_TIMER_ADDR:  ext_addrid_t := x"FFFFFFC";
-constant EXT_AC97_ADDR:   ext_addrid_t := x"FFFFFFD";
-constant EXT_UART_ADDR:   ext_addrid_t := x"FFFFFFE";
-constant EXT_GPMP_ADDR:    ext_addrid_t := x"FFFFFFF";
+
+
+
+
+
 --RS232
 constant UART_WIDTH : integer := 8;
 subtype uart_data is std_logic_vector(UART_WIDTH-1 downto 0);
+constant BAUD_RATE_WIDTH : integer := 16;
+subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
 --CLKs
-constant CLK_FREQ_MHZ : real := 33.33;
-constant BAUD_RATE : integer := 115200;
-constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
+--constant CLK_FREQ_MHZ : real := 33.33;
+--constant BAUD_RATE : integer := 115200;
+--constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
+-- constant CLK_PER_BAUD : integer := 434;
+constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud
+-- constant CLK_PER_BAUD : integer := 50; -- @modelsim
 
  component extension_uart is
         --some modules won't need all inputs/outputs
@@ -60,14 +39,20 @@ constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAU
 		-- general extension interface			
 			ext_reg  : in extmod_rec;
 			data_out : out gp_register_t;
-		-- Input
 
+			uart_int : out std_logic;
+		-- Input
+			bus_rx : in std_logic;
 		-- Ouput
 			bus_tx : out std_logic
 		);
  end component extension_uart;
 
 component rs232_tx is
+	generic	(
+		-- active reset value
+		RESET_VALUE : std_logic
+		);
 
 	port(
 		--System inputs
@@ -80,8 +65,34 @@ component rs232_tx is
 		--From/to sendlogic
 		new_tx_data : in std_logic;
 		tx_data : in uart_data;
-		tx_rdy : out std_logic
-	);
+		tx_rdy : out std_logic;
+		bd_rate : in baud_rate_l;
+		stop_bit : in std_logic	
+);
 end component rs232_tx;
 
+component rs232_rx is
+	generic	(
+		-- active reset value
+		RESET_VALUE : std_logic;
+		SYNC_STAGES : integer range 2 to integer'high
+		);
+
+	port(
+		--System inputs
+		sys_clk : in std_logic;
+		sys_res_n : in std_logic;
+
+		--Bus
+		bus_rx_unsync : in std_logic;
+
+		--To sendlogic
+		new_rx_data : out std_logic;
+		rx_data : out uart_data;
+		bd_rate : in baud_rate_l
+	);
+end component rs232_rx;
+
+
+
 end package extension_uart_pkg;