X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fextension_uart_pkg.vhd;h=1bbe2b892096fd4404a5bafa13dec520f989e659;hb=ea11b8a1f00f62aed7584f257f0a8a90e982a707;hp=c9892bdf1bab2e47beb339f35109297f8380fd9b;hpb=4d230c21bb8c9c23c3dd3349f8736b84987eab0d;p=calu.git

diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd
index c9892bd..1bbe2b8 100644
--- a/cpu/src/extension_uart_pkg.vhd
+++ b/cpu/src/extension_uart_pkg.vhd
@@ -16,19 +16,22 @@ package extension_uart_pkg is
 --RS232
 constant UART_WIDTH : integer := 8;
 subtype uart_data is std_logic_vector(UART_WIDTH-1 downto 0);
-constant BAUD_RATE_WITH : integer := 16;
-subtype baud_rate_l is std_logic_vector(BAUD_RATE_WITH-1 downto 0);
+constant BAUD_RATE_WIDTH : integer := 16;
+subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
 --CLKs
-constant CLK_FREQ_MHZ : real := 33.33;
-constant BAUD_RATE : integer := 115200;
+--constant CLK_FREQ_MHZ : real := 33.33;
+--constant BAUD_RATE : integer := 115200;
 --constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
-constant CLK_PER_BAUD : integer := 16330000;
+-- constant CLK_PER_BAUD : integer := 434;
+-- constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud
+-- constant CLK_PER_BAUD : integer := 50; -- @modelsim
 
  component extension_uart is
         --some modules won't need all inputs/outputs
 	generic	(
 			-- active reset value
-			RESET_VALUE : std_logic
+			RESET_VALUE : std_logic;
+			CLK_PER_BAUD : integer
 			);
 	port(
 		--System inputs
@@ -37,8 +40,10 @@ constant CLK_PER_BAUD : integer := 16330000;
 		-- general extension interface			
 			ext_reg  : in extmod_rec;
 			data_out : out gp_register_t;
-		-- Input
 
+			uart_int : out std_logic;
+		-- Input
+			bus_rx : in std_logic;
 		-- Ouput
 			bus_tx : out std_logic
 		);
@@ -67,4 +72,28 @@ component rs232_tx is
 );
 end component rs232_tx;
 
+component rs232_rx is
+	generic	(
+		-- active reset value
+		RESET_VALUE : std_logic;
+		SYNC_STAGES : integer range 2 to integer'high
+		);
+
+	port(
+		--System inputs
+		sys_clk : in std_logic;
+		sys_res_n : in std_logic;
+
+		--Bus
+		bus_rx_unsync : in std_logic;
+
+		--To sendlogic
+		new_rx_data : out std_logic;
+		rx_data : out uart_data;
+		bd_rate : in baud_rate_l
+	);
+end component rs232_rx;
+
+
+
 end package extension_uart_pkg;