X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fextension_uart_b.vhd;h=99278a970284bbf806e13c099c2b001745693660;hb=8e24e8c2dd4dbc06bb3c243e9ada320540738c69;hp=97fa9fbc89cba19c9dbd7aebd02413dfa8d7b83e;hpb=3e9337b7a4d81fb059f90716d7df9aa3bec9d719;p=calu.git

diff --git a/cpu/src/extension_uart_b.vhd b/cpu/src/extension_uart_b.vhd
index 97fa9fb..99278a9 100644
--- a/cpu/src/extension_uart_b.vhd
+++ b/cpu/src/extension_uart_b.vhd
@@ -15,6 +15,10 @@ signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send,
 signal new_bus_rx,new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
 signal 	bd_rate : baud_rate_l;
 signal rx_data : std_logic_vector(7 downto 0);
+
+signal uart_int_nxt : std_logic;
+signal uart_data_read_nxt : std_logic;
+
 begin
 
 
@@ -35,12 +39,13 @@ port map(
 	w3_uart_send(byte_t'range),
 	tx_rdy,
 	bd_rate,
-	w1_st_co(0)
+	w1_st_co(16)
 );
 
 rs232_rx_inst : rs232_rx
 generic	map(
-		RESET_VALUE
+		RESET_VALUE,
+		2
 		)
 port map(
 	--System inputs
@@ -61,34 +66,36 @@ port map(
 
 syn : process (clk, reset)
 begin
-        if (reset = RESET_VALUE) then
-		w1_st_co <= (others=>'0');
-		w2_uart_config(31 downto 16) <= (others=>'0');
-		-- todo mit einer konstante versehen
-		w2_uart_config(15 downto 0) <= x"01B2";
-		w3_uart_send <= (others=>'0');
-		w4_uart_receive <= (others=>'0');
-		tx_rdy_int <= '0';
-		new_tx_data <= '0';
-
-        elsif rising_edge(clk) then            
-		w1_st_co <= w1_st_co_nxt;
-		w2_uart_config <= w2_uart_config_nxt;
-		w3_uart_send <= w3_uart_send_nxt;
-		w4_uart_receive <= w4_uart_receive_nxt;
-		new_tx_data <= new_tx_data_nxt;
-		tx_rdy_int <= tx_rdy;
-        end if;
+   if (reset = RESET_VALUE) then
+			w1_st_co <= (others=>'0');
+			w2_uart_config(31 downto 16) <= (others=>'0');
+			w2_uart_config(15 downto 0) <= std_logic_vector(to_unsigned(CLK_PER_BAUD, 16));
+			w3_uart_send <= (others=>'0');
+			w4_uart_receive <= (others=>'0');
+			tx_rdy_int <= '0';
+			new_tx_data <= '0';
+			uart_int <= '0';
+
+	elsif rising_edge(clk) then            
+			w1_st_co <= w1_st_co_nxt;
+			w2_uart_config <= w2_uart_config_nxt;
+			w3_uart_send <= w3_uart_send_nxt;
+			w4_uart_receive <= w4_uart_receive_nxt;
+			new_tx_data <= new_tx_data_nxt;
+			tx_rdy_int <= tx_rdy;
+			uart_int <= uart_int_nxt;
+   end if;
 end process syn;
 
 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
 
-gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx)
+gwriten : process
+	(ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read_nxt)
 
 variable tmp_data  : gp_register_t;
 
 begin
-
+		uart_int_nxt <= '0';
 		w1_st_co_nxt <= w1_st_co;
 		w2_uart_config_nxt <= w2_uart_config;
 		w3_uart_send_nxt <= w3_uart_send;
@@ -115,7 +122,7 @@ begin
 		when "01" =>
 			w2_uart_config_nxt <= tmp_data;
 		when "10" =>
-			w1_st_co_nxt(16) <= '1'; -- busy flag set
+			w1_st_co_nxt(0) <= '1'; -- busy flag set
 			w3_uart_send_nxt <= tmp_data;
 		when "11" =>
 			--w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
@@ -124,15 +131,19 @@ begin
 	end if;
 
 	if  tx_rdy = '1' and tx_rdy_int = '0' then
-		w1_st_co_nxt(16) <= '0'; -- busy flag reset	
+		w1_st_co_nxt(0) <= '0'; -- busy flag reset	
 	end if;
 
 	if new_bus_rx = '1' then
 		w4_uart_receive_nxt(7 downto 0) <= rx_data;
-		w1_st_co_nxt(17) <= '1';
+		w1_st_co_nxt(1) <= '1';
+		uart_int_nxt <= '1';
+	end if;
+	
+	if (uart_data_read_nxt = '1' and w1_st_co(1) = '1' and ext_reg.sel = '1') then
+		w1_st_co_nxt(1) <= '0';
 	end if;
 	
-
 end process gwriten;
 
 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
@@ -140,6 +151,9 @@ gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receiv
 variable tmp_data  : gp_register_t;
 
 begin
+
+	uart_data_read_nxt <= '0';
+
 	if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
 		case ext_reg.addr(1 downto 0) is
 		when "00" => 
@@ -188,7 +202,8 @@ begin
 			end if;
 			data_out <= tmp_data;
 		when "11" =>
-			tmp_data := (others =>'0');			
+			tmp_data := (others =>'0');	
+			uart_data_read_nxt <= '1';
 			if ext_reg.byte_en(0) = '1' then
 				tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
 			end if;