X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fextension_uart_b.vhd;h=99278a970284bbf806e13c099c2b001745693660;hb=8e24e8c2dd4dbc06bb3c243e9ada320540738c69;hp=95e761b84b9f1673b0b2274f0d06cd9b230ff015;hpb=2d98d2f7b3eaa3afc1cc264725b2596184f1e6e3;p=calu.git

diff --git a/cpu/src/extension_uart_b.vhd b/cpu/src/extension_uart_b.vhd
index 95e761b..99278a9 100644
--- a/cpu/src/extension_uart_b.vhd
+++ b/cpu/src/extension_uart_b.vhd
@@ -12,8 +12,12 @@ use work.extension_uart_pkg.all;
 architecture behav of extension_uart is
 
 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
-signal new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
+signal new_bus_rx,new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
 signal 	bd_rate : baud_rate_l;
+signal rx_data : std_logic_vector(7 downto 0);
+
+signal uart_int_nxt : std_logic;
+signal uart_data_read_nxt : std_logic;
 
 begin
 
@@ -35,39 +39,68 @@ port map(
 	w3_uart_send(byte_t'range),
 	tx_rdy,
 	bd_rate,
-	w1_st_co(0)
+	w1_st_co(16)
 );
 
+rs232_rx_inst : rs232_rx
+generic	map(
+		RESET_VALUE,
+		2
+		)
+port map(
+	--System inputs
+	clk,
+	reset,
+
+	--Bus
+	bus_rx,
+
+	--From/to sendlogic
+	new_bus_rx,
+	rx_data,
+	bd_rate
+);
 
 
 
 
 syn : process (clk, reset)
 begin
-        if (reset = RESET_VALUE) then
-		w1_st_co <= (others=>'0');
-		w2_uart_config <= (others=>'0');
-		w3_uart_send <= (others=>'0');
-		w4_uart_receive <= (others=>'0');
-
-
-        elsif rising_edge(clk) then            
-		w1_st_co <= w1_st_co_nxt;
-		w2_uart_config <= w2_uart_config_nxt;
-		w3_uart_send <= w3_uart_send_nxt;
-		w4_uart_receive <= w4_uart_receive_nxt;
-		new_tx_data <= new_tx_data_nxt;
-		tx_rdy_int <= tx_rdy;
-        end if;
+   if (reset = RESET_VALUE) then
+			w1_st_co <= (others=>'0');
+			w2_uart_config(31 downto 16) <= (others=>'0');
+			w2_uart_config(15 downto 0) <= std_logic_vector(to_unsigned(CLK_PER_BAUD, 16));
+			w3_uart_send <= (others=>'0');
+			w4_uart_receive <= (others=>'0');
+			tx_rdy_int <= '0';
+			new_tx_data <= '0';
+			uart_int <= '0';
+
+	elsif rising_edge(clk) then            
+			w1_st_co <= w1_st_co_nxt;
+			w2_uart_config <= w2_uart_config_nxt;
+			w3_uart_send <= w3_uart_send_nxt;
+			w4_uart_receive <= w4_uart_receive_nxt;
+			new_tx_data <= new_tx_data_nxt;
+			tx_rdy_int <= tx_rdy;
+			uart_int <= uart_int_nxt;
+   end if;
 end process syn;
 
 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
 
-gwriten : process (ext_reg,tx_rdy)
+gwriten : process
+	(ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read_nxt)
 
 variable tmp_data  : gp_register_t;
 
 begin
+		uart_int_nxt <= '0';
+		w1_st_co_nxt <= w1_st_co;
+		w2_uart_config_nxt <= w2_uart_config;
+		w3_uart_send_nxt <= w3_uart_send;
+		w4_uart_receive_nxt <= w4_uart_receive;
+
 	if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
 		tmp_data := (others =>'0');			
 		if ext_reg.byte_en(0) = '1' then
@@ -89,30 +122,38 @@ begin
 		when "01" =>
 			w2_uart_config_nxt <= tmp_data;
 		when "10" =>
-			w1_st_co_nxt(16) <= '1'; -- busy flag set
+			w1_st_co_nxt(0) <= '1'; -- busy flag set
 			w3_uart_send_nxt <= tmp_data;
 		when "11" =>
-			w4_uart_receive_nxt <= tmp_data;
+			--w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
 		when others => null;
 		end case;
-	else
-		w1_st_co_nxt <= w1_st_co;
-		w2_uart_config_nxt <= w2_uart_config;
-		w3_uart_send_nxt <= w3_uart_send;
-		w4_uart_receive_nxt <= w4_uart_receive;
 	end if;
 
 	if  tx_rdy = '1' and tx_rdy_int = '0' then
-		w1_st_co_nxt(16) <= '0'; -- busy flag reset	
+		w1_st_co_nxt(0) <= '0'; -- busy flag reset	
 	end if;
 
+	if new_bus_rx = '1' then
+		w4_uart_receive_nxt(7 downto 0) <= rx_data;
+		w1_st_co_nxt(1) <= '1';
+		uart_int_nxt <= '1';
+	end if;
+	
+	if (uart_data_read_nxt = '1' and w1_st_co(1) = '1' and ext_reg.sel = '1') then
+		w1_st_co_nxt(1) <= '0';
+	end if;
+	
 end process gwriten;
 
-gread : process (clk,ext_reg)
+gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
 
 variable tmp_data  : gp_register_t;
 
 begin
+
+	uart_data_read_nxt <= '0';
+
 	if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
 		case ext_reg.addr(1 downto 0) is
 		when "00" => 
@@ -161,7 +202,8 @@ begin
 			end if;
 			data_out <= tmp_data;
 		when "11" =>
-			tmp_data := (others =>'0');			
+			tmp_data := (others =>'0');	
+			uart_data_read_nxt <= '1';
 			if ext_reg.byte_en(0) = '1' then
 				tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
 			end if;
@@ -187,7 +229,7 @@ end process gread;
 
 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
 
-dataprocess : process (ext_reg,tx_rdy)
+dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
 
 
 begin