X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fextension_pkg.vhd;h=3d18a1998204a519dd7c3544977e5eea82fe3e2a;hb=1968f329b10681b760faec9369aa893cd2af8d44;hp=49d5cdbae5e214369faa08c6ef33130a6cca6f6d;hpb=2271e17a13449f5e4f590cca7dc9c1c2992cb30c;p=calu.git

diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd
index 49d5cdb..3d18a19 100644
--- a/cpu/src/extension_pkg.vhd
+++ b/cpu/src/extension_pkg.vhd
@@ -1,42 +1,74 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
-use work.alu_pkg.all;
-use work.gpm_pkg.all;
+--use work.alu_pkg.all;
+--use work.gpm_pkg.all;
 
 package extension_pkg is
 
 constant EXTWORDL : integer := log2c(4);
 constant BYTEADDR : integer := log2c(4);
-constant PCOUNT   : integer := log2c(4);
+constant PCOUNT   : integer := 3;
 constant EXTWORDS : integer := EXTWORDL + BYTEADDR;
 
 subtype ext_addrid_t  is std_logic_vector(gp_register_t'high - EXTWORDS downto 0);
 subtype ext_addr_t    is std_logic_vector((gp_register_t'high-BYTEADDR) downto 0);    
-subtype pointer_count is std_logic_vector(PCOUNT-1 downto 0);   
+subtype paddr_t is std_logic_vector(log2c(PCOUNT)-1 downto 0);   
 
         type extmod_rec is record
                 sel   : std_logic;
                 wr_en : std_logic;
-                byte_en : std_logic_vector(gp_register_t'length/byte_t'length-1 downto 0); 
+                byte_en : byte_en_t;
                 data : gp_register_t;
                 addr : ext_addr_t;     
         end record; 
 
 
+type status_rec is record
+		zero : std_logic;
+		oflo : std_logic;
+		sign : std_logic;
+		carry : std_logic;
+end record;
 
+procedure put_word_be (tmp : out gp_register_t; signal reg : in gp_register_t; signal byte_en : byte_en_t);
 
-constant EXT_7SEG_ADDR:   ext_addrid_t := x"FFFFFFA";
+-- Addressen der bis jetzt vorhanden extensions
+constant EXT_UART_ADDR:   ext_addrid_t := x"0000200";
+constant EXT_7SEG_ADDR:   ext_addrid_t := x"0000201";
+constant EXT_INT_ADDR:	  ext_addrid_t := x"0000202";
+constant EXT_IMP_ADDR:	  ext_addrid_t := x"0000203";
+constant EXT_TIMER_ADDR:  ext_addrid_t := x"0000204";
+-- dummy addressen
 constant EXT_EXTMEM_ADDR: ext_addrid_t := x"FFFFFFB";
-constant EXT_TIMER_ADDR:  ext_addrid_t := x"FFFFFFC";
 constant EXT_AC97_ADDR:   ext_addrid_t := x"FFFFFFD";
-constant EXT_UART_ADDR:   ext_addrid_t := x"FFFFFFE";
 constant EXT_GPMP_ADDR:    ext_addrid_t := x"FFFFFFF";
 
- component extension_gpm is
+component extension_gpm is
         --some modules won't need all inputs/outputs
 	generic	(
 			-- active reset value
@@ -46,18 +78,51 @@ constant EXT_GPMP_ADDR:    ext_addrid_t := x"FFFFFFF";
 		--System inputs
 			clk :   in std_logic;
 			reset : in std_logic;
-		-- Standartinterface			
+		-- general extension interface			
 			ext_reg  : in extmod_rec;
-			data_out : out gp_register_t;
+			 data_out : out gp_register_t;
 		-- Input
-			alu_nxt : in alu_result_rec;
+			psw_nxt : in status_rec;
+			paddr 	: in paddr_t;
+			pinc	: in std_logic;
+			pwr_en  : in std_logic;
 		-- Ouput
-			 psw     : out status_rec
-
-			
+			 psw     : out status_rec;
+			 pval	 : out gp_register_t;
+			 pval_nxt : out gp_register_t
 		);
  end component extension_gpm;
 
+component extension_interrupt is
+        --some modules won't need all inputs/outputs
+	generic	(
+			-- active reset value
+			RESET_VALUE : std_logic
+			);
+	port(
+		--System inputs
+			clk :   in std_logic;
+			reset : in std_logic;
+		-- general extension interface			
+			ext_reg  : in extmod_rec;
+			data_out : out gp_register_t;
+		-- Input
+			uart_int : in std_logic;
+		-- Ouput
+			int_req : out interrupt_t
+		);
+ end component extension_interrupt;
 
 
 end package extension_pkg;
+
+package body extension_pkg is
+	procedure put_word_be (tmp : out gp_register_t; signal reg : in gp_register_t; signal byte_en : byte_en_t) is
+	begin
+		for i in 0 to 3 loop
+			if byte_en(i) = '1' then
+				tmp(((i+1)*byte_t'length-1) downto i*byte_t'length) := reg(((i+1)*byte_t'length-1) downto i*byte_t'length);
+			end if;
+		end loop;
+	end;
+end package body extension_pkg;