X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fextension_b.vhd;h=593c40af9f0029b2ad0ebc60645f07f1bf11dc0d;hb=1968f329b10681b760faec9369aa893cd2af8d44;hp=d004bbb5c8834396d985d9ee849ea325a3eeaa3a;hpb=f4f734f50124027f0371a3cb5f4de18353692235;p=calu.git

diff --git a/cpu/src/extension_b.vhd b/cpu/src/extension_b.vhd
index d004bbb..593c40a 100644
--- a/cpu/src/extension_b.vhd
+++ b/cpu/src/extension_b.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
@@ -25,20 +46,21 @@ syn : process (clk, reset)
 begin
         if (reset = RESET_VALUE) then
                 reg.status <= (others=>'0');
-		reg.pointers <= (others => (std_logic_vector(to_unsigned(DATA_END_ADDR,DATA_ADDR_WIDTH)));
+		reg.preg <= (others => (std_logic_vector(to_unsigned(DATA_END_ADDR,reg.preg(0)'length))));
         elsif rising_edge(clk) then
                 reg <= reg_nxt;
         end if;
 end process syn;
 
-asyn : process (clk, reset, reg, psw_nxt, ext_reg, pval, pwr_en, pinc, paddr)
+asyn : process (clk, reset, reg, psw_nxt, ext_reg, pwr_en, pinc, paddr)
 	variable reg_nxt_v : gpm_internal;
-	variable incb : gp_register_t;
-	variable sel_pval : gp_register_t;
+	variable incb : ext_addr_t;
+	variable sel_pval, sel_pval_nxt : ext_addr_t;
 	
 	variable data_out_v : gp_register_t;
 	variable data_v : gp_register_t;
 	variable tmp_data  : gp_register_t;
+	
 begin
 	reg_nxt_v := reg;
 	data_v  := ext_reg.data;
@@ -53,56 +75,11 @@ begin
 	else
 		incb(incb'high downto 1) := (others => '0');
 	end if;
-	
-	if (ext_reg.sel = '1') and ext_reg.wr_en = '1' then
-		case ext_reg.addr(1 downto 0) is
-		when "00" => 
-			if ext_reg.byte_en(0) = '1' then
-				reg_nxt_v.psw := (data_v(0), data_v(1), data_v(3), data_v(2));
-				psw <= reg_nxt_v.psw;
-			end if;
-		when "01" =>
-			--STACK_POINTER
-			tmp_data := (others =>'0');
-			tmp_data(tmp_data'high downto BYTE_ADDR) := reg.preg(0);
-			
-			if ext_reg.byte_en(0) = '1' then
-				tmp_data(byte_t'range) := data_v(byte_t'range);
-			end if;
-			if ext_reg.byte_en(1) = '1' then
-				tmp_data((2*byte_t'length-1) downto byte_t'length) := data_v(2*byte_t'length-1) downto byte_t'length);
-			end if;
-			if ext_reg.byte_en(2) = '1' then
-				tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := data_v(3*byte_t'length-1) downto 2*byte_t'length);
-			end if;
-			if ext_reg.byte_en(3) = '1' then
-				tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := data_v(4*byte_t'length-1) downto 3*byte_t'length);
-			end if;
-			
-			reg_nxt_v.preg(0) := tmp_data(tmp_data'high downto BYTE_ADDR);
-		when others => null;
-		end case;
-	end if;
-	
-	
-	if (ext_reg.sel = '1') and wr_en = '0' then
-		case ext_reg.addr(1 downto 0) is
-		when "00" => 
-			if ext_reg.byte_en(0) = '1' then
-				data_out_v(3 downto 0) <= (reg.status.sign, reg.status.carry, reg.status.oflo, reg.status.zero);
-			end if;
-		when "01" =>
-			--STACK_POINTER
-			data_out_v(data_out_v'high downto BYTE_ADDR) := reg.preg(0);
-		when others => null;
-		end case;
-	end if;
 
-
-	sel_pval := reg_nxt_v.preg(unsigned(paddr));
-	
+	sel_pval:= reg_nxt_v.preg(0);
+	sel_pval_nxt := std_logic_vector(unsigned(sel_pval)+unsigned(incb));
 	if pwr_en = '1' then
-		reg_nxt_v.preg(to_integer(unsigned(paddr))) := std_logic_vector(unsigned(sel_pval)+unsigned(incb));
+		reg_nxt_v.preg(0) := sel_pval_nxt;
 	end if;
 
 	reg_nxt_v.status := psw_nxt;
@@ -111,7 +88,9 @@ begin
 	data_out <= data_out_v;
 	
 	pval <= (others =>'0');
-	pval(pval'high downto BYTE_ADDR) <= sel_pval;
+	pval(pval'high downto BYTEADDR) <= sel_pval;
+	pval_nxt <= (others =>'0');
+	pval_nxt(pval'high downto BYTEADDR) <= sel_pval_nxt;
 end process asyn;
 
 end behav;