X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fextension_7seg_b.vhd;h=db30e24e78ee61cfa5632f7515146ad1512e73cb;hb=1968f329b10681b760faec9369aa893cd2af8d44;hp=0e58cca78a7924b6c4cd4836f41b06742823407b;hpb=8dd0b1556d1726952e776954a6b2ca9ae357491c;p=calu.git

diff --git a/cpu/src/extension_7seg_b.vhd b/cpu/src/extension_7seg_b.vhd
index 0e58cca..db30e24 100755
--- a/cpu/src/extension_7seg_b.vhd
+++ b/cpu/src/extension_7seg_b.vhd
@@ -1,86 +1,111 @@
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
---use work.math_pkg.all;
-use work.common_pkg.all;
-use work.core_pkg.all;
-
-use work.mem_pkg.all;
-use work.extension_pkg.all;
-use work.extension_7seg_pkg.all;
-
-architecture behav of extension_7seg is
-
-signal s_state, s_state_nxt : sseg_state_rec;
-signal ext_reg_r  : extmod_rec;
-
-begin
-
-seg_syn: process(sys_clk, sys_res_n)
-
-begin
-
-	if (sys_res_n = RESET_VALUE) then
-		
-		s_state.digit0 <= (others => '0');--set(0,7);
-		s_state.digit1 <= (others => '0');--set(0,7);
-		s_state.digit2 <= (others => '0');--set(0,7);
-		s_state.digit3 <= (others => '0');--set(0,7);
-
-		ext_reg_r.sel <='0';
-		ext_reg_r.wr_en <= '0';
-		ext_reg_r.byte_en <= (others => '0');
-		ext_reg_r.data <= (others => '0');
-		ext_reg_r.addr <= (others => '0');
-		
-	elsif rising_edge(sys_clk) then
-		
-		s_state <= s_state_nxt;
-		ext_reg_r <= ext_reg;
-		
-	end if;
-	
-end process; 
-
-seg_asyn: process(s_state, ext_reg_r)	
-
-variable tmp_data  : byte_t;
-
-begin
-	s_state_nxt <= s_state;	
-	tmp_data := (others =>'0');			
-
-	if ext_reg_r.sel = '1' and ext_reg_r.wr_en = '1' then
-
-		tmp_data(byte_t'range) :=ext_reg_r.data(byte_t'range);
-
-		s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));
-		s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));
-		s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));
-		s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));
-
-		case ext_reg_r.byte_en(1 downto 0) is
-		when "01" => s_state_nxt.digit3 <= digit_decode("11111");
-		when "00" => null;
-		when "10" => null;
-		when "11" => null;
-		when others => null;
-		end case;
-
-
-	end if;
-
-end process; --ps2_next
-
-seg_out: process(s_state)
-begin
-	
-	o_digit0 <= not(s_state.digit0);
-	o_digit1 <= not(s_state.digit1);
-	o_digit2 <= not(s_state.digit2);
-	o_digit3 <= not(s_state.digit3);
-
-end process;
-
-end behav;
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--use work.math_pkg.all;
+use work.common_pkg.all;
+use work.core_pkg.all;
+
+use work.mem_pkg.all;
+use work.extension_pkg.all;
+use work.extension_7seg_pkg.all;
+
+architecture behav of extension_7seg is
+
+signal s_state, s_state_nxt : sseg_state_rec;
+signal ext_reg_r  : extmod_rec;
+
+begin
+
+seg_syn: process(sys_clk, sys_res_n)
+
+begin
+
+	if (sys_res_n = RESET_VALUE) then
+		
+		s_state.digit0 <= (others => '0');--set(0,7);
+		s_state.digit1 <= (others => '0');--set(0,7);
+		s_state.digit2 <= (others => '0');--set(0,7);
+		s_state.digit3 <= (others => '0');--set(0,7);
+
+		ext_reg_r.sel <='0';
+		ext_reg_r.wr_en <= '0';
+		ext_reg_r.byte_en <= (others => '0');
+		ext_reg_r.data <= (others => '0');
+		ext_reg_r.addr <= (others => '0');
+		
+	elsif rising_edge(sys_clk) then
+		
+		s_state <= s_state_nxt;
+		ext_reg_r <= ext_reg;
+		
+	end if;
+	
+end process; 
+
+seg_asyn: process(s_state, ext_reg_r)	
+
+begin
+	s_state_nxt <= s_state;	
+
+	if ext_reg_r.sel = '1' and ext_reg_r.wr_en = '1' then
+
+
+--		case ext_reg_r.byte_en(1 downto 0) is
+--		when "00" => null;
+--			s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));
+--			s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));
+--			s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));
+--			s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));
+--		when others => 
+--			s_state_nxt.digit0 <= (others => '1');
+--			s_state_nxt.digit1 <= (others => '1');
+--			s_state_nxt.digit2 <= (others => '1');
+--			s_state_nxt.digit3 <= (others => '1');
+--		end case;
+
+		if (ext_reg_r.byte_en(0) = '1') then
+			s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));
+			s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));
+		end if;
+		if (ext_reg_r.byte_en(1) = '1') then
+			s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));
+			s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));
+		end if;
+
+	end if;
+
+end process; --ps2_next
+
+seg_out: process(s_state)
+begin
+	
+	o_digit0 <= not(s_state.digit0);
+	o_digit1 <= not(s_state.digit1);
+	o_digit2 <= not(s_state.digit2);
+	o_digit3 <= not(s_state.digit3);
+
+end process;
+
+end behav;