X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fextension_7seg_b.vhd;h=2ac967a495331b3654ba0d27685f98088473d8aa;hb=64ef7ca2830116409f4c23802a202ab4b1ce5ec8;hp=a78da17d9339f43a4a09ddacaa2714d60d606267;hpb=cde0d011bc1b001e7d6bd5b9d3d3678e4cd7e2e7;p=calu.git

diff --git a/cpu/src/extension_7seg_b.vhd b/cpu/src/extension_7seg_b.vhd
index a78da17..2ac967a 100755
--- a/cpu/src/extension_7seg_b.vhd
+++ b/cpu/src/extension_7seg_b.vhd
@@ -1,82 +1,90 @@
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
---use work.math_pkg.all;
-use work.common_pkg.all;
-use work.core_pkg.all;
-
-use work.mem_pkg.all;
-use work.extension_pkg.all;
-use work.extension_7seg_pkg.all;
-
-architecture behav of extension_7seg is
-
-signal s_state, s_state_nxt : sseg_state_rec;
-signal ext_reg_r  : extmod_rec;
-
-begin
-
-seg_syn: process(sys_clk, sys_res_n)
-
-begin
-
-	if (sys_res_n = RESET_VALUE) then
-		
-		s_state.digit0 <= (others => '0');--set(0,7);
-		s_state.digit1 <= (others => '0');--set(0,7);
-		s_state.digit2 <= (others => '0');--set(0,7);
-		s_state.digit3 <= (others => '0');--set(0,7);
-
-		ext_reg_r.sel <='0';
-		ext_reg_r.wr_en <= '0';
-		ext_reg_r.byte_en <= (others => '0');
-		ext_reg_r.data <= (others => '0');
-		ext_reg_r.addr <= (others => '0');
-		
-	elsif rising_edge(sys_clk) then
-		
-		s_state <= s_state_nxt;
-		ext_reg_r <= ext_reg;
-		
-	end if;
-	
-end process; 
-
-seg_asyn: process(s_state, ext_reg_r)	
-
-begin
-	s_state_nxt <= s_state;	
-
-	if ext_reg_r.sel = '1' and ext_reg_r.wr_en = '1' then
-
-
-		case ext_reg_r.byte_en(1 downto 0) is
-		when "00" => null;
-			s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));
-			s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));
-			s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));
-			s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));
-		when others => 
-			s_state_nxt.digit0 <= (others => '1');
-			s_state_nxt.digit1 <= (others => '1');
-			s_state_nxt.digit2 <= (others => '1');
-			s_state_nxt.digit3 <= (others => '1');
-		end case;
-
-
-	end if;
-
-end process; --ps2_next
-
-seg_out: process(s_state)
-begin
-	
-	o_digit0 <= not(s_state.digit0);
-	o_digit1 <= not(s_state.digit1);
-	o_digit2 <= not(s_state.digit2);
-	o_digit3 <= not(s_state.digit3);
-
-end process;
-
-end behav;
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--use work.math_pkg.all;
+use work.common_pkg.all;
+use work.core_pkg.all;
+
+use work.mem_pkg.all;
+use work.extension_pkg.all;
+use work.extension_7seg_pkg.all;
+
+architecture behav of extension_7seg is
+
+signal s_state, s_state_nxt : sseg_state_rec;
+signal ext_reg_r  : extmod_rec;
+
+begin
+
+seg_syn: process(sys_clk, sys_res_n)
+
+begin
+
+	if (sys_res_n = RESET_VALUE) then
+		
+		s_state.digit0 <= (others => '0');--set(0,7);
+		s_state.digit1 <= (others => '0');--set(0,7);
+		s_state.digit2 <= (others => '0');--set(0,7);
+		s_state.digit3 <= (others => '0');--set(0,7);
+
+		ext_reg_r.sel <='0';
+		ext_reg_r.wr_en <= '0';
+		ext_reg_r.byte_en <= (others => '0');
+		ext_reg_r.data <= (others => '0');
+		ext_reg_r.addr <= (others => '0');
+		
+	elsif rising_edge(sys_clk) then
+		
+		s_state <= s_state_nxt;
+		ext_reg_r <= ext_reg;
+		
+	end if;
+	
+end process; 
+
+seg_asyn: process(s_state, ext_reg_r)	
+
+begin
+	s_state_nxt <= s_state;	
+
+	if ext_reg_r.sel = '1' and ext_reg_r.wr_en = '1' then
+
+
+--		case ext_reg_r.byte_en(1 downto 0) is
+--		when "00" => null;
+--			s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));
+--			s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));
+--			s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));
+--			s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));
+--		when others => 
+--			s_state_nxt.digit0 <= (others => '1');
+--			s_state_nxt.digit1 <= (others => '1');
+--			s_state_nxt.digit2 <= (others => '1');
+--			s_state_nxt.digit3 <= (others => '1');
+--		end case;
+
+		if (ext_reg_r.byte_en(0) = '1') then
+			s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));
+			s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));
+		end if;
+		if (ext_reg_r.byte_en(1) = '1') then
+			s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));
+			s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));
+		end if;
+
+	end if;
+
+end process; --ps2_next
+
+seg_out: process(s_state)
+begin
+	
+	o_digit0 <= not(s_state.digit0);
+	o_digit1 <= not(s_state.digit1);
+	o_digit2 <= not(s_state.digit2);
+	o_digit3 <= not(s_state.digit3);
+
+end process;
+
+end behav;