X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fexec_op%2Fadd_op_b.vhd;h=eb64b6907e6c6f94e28a39fb8cae0545ae4a28b1;hb=1968f329b10681b760faec9369aa893cd2af8d44;hp=88e34d432b75e0ba2cf046959ef60f3e8e7a1e67;hpb=51ceb8fbeead4e281090bffefd2d9f1757c23955;p=calu.git

diff --git a/cpu/src/exec_op/add_op_b.vhd b/cpu/src/exec_op/add_op_b.vhd
index 88e34d4..eb64b69 100644
--- a/cpu/src/exec_op/add_op_b.vhd
+++ b/cpu/src/exec_op/add_op_b.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
@@ -23,37 +44,46 @@ calc: process(left_operand, right_operand, alu_state, sub, addc)
 	variable addcarry		: unsigned(carry_res'range);
 begin
 		alu_result_v := alu_state;
-		
-		addcarry := (others =>'0');
-		addcarry(0) := alu_state.status.carry and addc;
-		
-		complement := inc(not(right_operand));
-		l_neg := left_operand(gp_register_t'high);
-		
-		carry_res := unsigned('0' & left_operand)+addcarry;
-		oflo1 := add_oflo(l_neg,'0',carry_res(gp_register_t'high));
-		
+		addcarry := (others => '0');
+		addcarry(0):= (alu_state.status.carry and addc) or (sub and not(addc));
 		if sub = '1' then
-			tmp_right_operand := unsigned('0' & complement);
+			carry_res := unsigned('0' & left_operand)+unsigned('0' & not(right_operand))+addcarry;
 		else
-			tmp_right_operand := unsigned('0' & right_operand);
+			carry_res := unsigned('0' & left_operand)+unsigned('0' & right_operand)+addcarry;
 		end if;
+		alu_result_v.result := std_logic_vector(carry_res(gp_register_t'range));
+		alu_result_v.status.carry := carry_res(carry_res'high);
+		alu_result_v.status.oflo := add_oflo(left_operand(gp_register_t'high),right_operand(gp_register_t'high) xor sub, carry_res(gp_register_t'high));
+		-- addcarry := (others =>'0');
+		-- addcarry(0) := alu_state.status.carry and addc;
 		
-		l_neg := carry_res(gp_register_t'high);
-		r_neg := tmp_right_operand(gp_register_t'high);
+		-- complement := inc(not(right_operand));
+		-- l_neg := left_operand(gp_register_t'high);
 		
-		carry_res := carry_res + tmp_right_operand;
-		oflo2 := add_oflo(l_neg,r_neg,carry_res(gp_register_t'high));
+		-- carry_res := unsigned('0' & left_operand)+addcarry;
+		-- oflo1 := add_oflo(l_neg,'0',carry_res(gp_register_t'high));
 		
-
-		alu_result_v.result := std_logic_vector(carry_res(gp_register_t'range));
-		alu_result_v.status.carry := carry_res(carry_res'high);
+		-- if sub = '1' then
+			-- tmp_right_operand := unsigned('0' & complement);
+		-- else
+			-- tmp_right_operand := unsigned('0' & right_operand);
+		-- end if;
 		
+		-- l_neg := carry_res(gp_register_t'high);
+		-- r_neg := tmp_right_operand(gp_register_t'high);
+		
+		-- carry_res := carry_res + tmp_right_operand;
+		-- oflo2 := add_oflo(l_neg,r_neg,carry_res(gp_register_t'high));
+		
+
+		-- alu_result_v.result := std_logic_vector(carry_res(gp_register_t'range));
+		-- alu_result_v.status.carry := carry_res(carry_res'high);
+	-- --	alu_result_v.result := (0 => '1', others => '0');
 		
-		alu_result_v.status.carry := oflo1 or oflo2;
+		-- alu_result_v.status.oflo := oflo1 or oflo2;
 		
-		--sign will be set globally.
-		--zero will be set globally.
+		-- --sign will be set globally.
+		-- --zero will be set globally.
 		
 		alu_result <= alu_result_v;
 end process;