X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fdecode_stage_b.vhd;h=37f6688e201885e57fb3d652cd0c097e262b7ed0;hb=7c21f901c3a852725bec1e9691627c3280ad6ae0;hp=7d42e8fdf9f56a829512f8072e8e163d331bdcad;hpb=9b61bb3513cd762f9714fb94ab434b4cbc616ea3;p=calu.git

diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd
index 7d42e8f..37f6688 100644
--- a/cpu/src/decode_stage_b.vhd
+++ b/cpu/src/decode_stage_b.vhd
@@ -66,7 +66,8 @@ begin
 		dec_op_inst.saddr1 <= (others => '0');
 		dec_op_inst.saddr2 <= (others => '0');
 		dec_op_inst.daddr <= (others => '0');
-
+		dec_op_inst.displacement <= (others => '0');
+		dec_op_inst.prog_cnt <= (others => '0');
 
 	elsif rising_edge(clk) then
 		rtw_rec <= rtw_rec_nxt;
@@ -92,7 +93,7 @@ end process;
 --	end record;
 
 -- output logic incl. bypassing reg-file
-output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data)
+output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data, nop)
 
 begin
 
@@ -100,11 +101,15 @@ begin
 	to_next_stage.src1 <= reg1_rd_data;
 	to_next_stage.src2 <= reg2_rd_data;
 
+	if (nop = '1') then
+		to_next_stage.condition <= "1111";
+	end if;
+
 end process;
 
 
 -- fills output register
-to_next: process(instr_spl)
+to_next: process(instr_spl, prog_cnt)
 
 begin
 	dec_op_inst_nxt.condition <= instr_spl.predicates;
@@ -116,6 +121,8 @@ begin
 	dec_op_inst_nxt.saddr2 <= instr_spl.reg_src2_addr;
 	dec_op_inst_nxt.daddr <= instr_spl.reg_dest_addr; --(others => '0');
 	dec_op_inst_nxt.op_group <= instr_spl.op_group;
+	dec_op_inst_nxt.displacement <= instr_spl.displacement;
+	dec_op_inst_nxt.prog_cnt <= prog_cnt;
 
 end process;
 
@@ -152,10 +159,11 @@ begin
 	rtw_rec_nxt.rtw_reg2 <= '0';
 	rtw_rec_nxt.immediate <= (others => '0');
 	rtw_rec_nxt.imm_set <= '0';
+--- ???? wieso
 	rtw_rec_nxt.reg1_addr <= instr_spl.reg_src1_addr;
 	rtw_rec_nxt.reg2_addr <= instr_spl.reg_src2_addr;
 
-	if (instr_spl.op_detail(IMM_OPT) = '1') then
+	if (instr_spl.op_detail(IMM_OPT) = '1') then -- or instr_spl.op_group = LDST_OP
 		rtw_rec_nxt.immediate <= instr_spl.immediate;
 		rtw_rec_nxt.imm_set <= '1';
 	end if;
@@ -164,7 +172,7 @@ begin
 		rtw_rec_nxt.rtw_reg1 <= ('1' and reg_we);
 	end if;
 
-	if (reg_w_addr = instr_spl.reg_src1_addr) then
+	if (reg_w_addr = instr_spl.reg_src2_addr) then
 		rtw_rec_nxt.rtw_reg2 <= ('1' and reg_we);
 	end if;
 
@@ -172,7 +180,7 @@ end process;
 
 
 -- async process: calculates branch prediction
-br_pred: process(instr_spl)
+br_pred: process(instr_spl, prog_cnt)
 
 begin
 
@@ -180,7 +188,11 @@ begin
 	branch_prediction_bit <= '0';
 
 	if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then
-		branch_prediction_res <= instr_spl.immediate;	--both 32 bit
+		if instr_spl.int = '0' then		
+			branch_prediction_res <= std_logic_vector(unsigned(instr_spl.immediate) + unsigned(prog_cnt));	--both 32 bit
+		else 
+			branch_prediction_res <= instr_spl.immediate;
+		end if;
 		branch_prediction_bit <= '1';
 	end if;