X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fdecode_stage.vhd;h=8fb9df140207c138813870bbcbd0efe6d56a6ce8;hb=1968f329b10681b760faec9369aa893cd2af8d44;hp=103822cb0463fef2d39433f637a01e5db047bede;hpb=65d0fb429344b9db6cd115842c8c534b1f05c20b;p=calu.git diff --git a/cpu/src/decode_stage.vhd b/cpu/src/decode_stage.vhd index 103822c..8fb9df1 100644 --- a/cpu/src/decode_stage.vhd +++ b/cpu/src/decode_stage.vhd @@ -1,3 +1,24 @@ +-- `Deep Thought', a softcore CPU implemented on a FPGA +-- +-- Copyright (C) 2010 Markus Hofstaetter +-- Copyright (C) 2010 Martin Perner +-- Copyright (C) 2010 Stefan Rebernig +-- Copyright (C) 2010 Manfred Schwarz +-- Copyright (C) 2010 Bernhard Urban +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . + library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; @@ -22,14 +43,16 @@ entity decode_stage is --Data inputs instruction : in instruction_word_t; + prog_cnt : in instruction_addr_t; reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0); reg_wr_data : in gp_register_t; reg_we : in std_logic; + nop : in std_logic; --Data outputs -- reg1_rd_data : out gp_register_t; -- reg2_rd_data : out gp_register_t; - branch_prediction_res : out instruction_word_t; + branch_prediction_res : out instruction_addr_t; branch_prediction_bit : out std_logic; to_next_stage : out dec_op