X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fdecode_stage.vhd;h=620a2ccdbf048113e0b4c9b04187b052e19ba816;hb=0ba0c7effbaf554ad42db51334581859a0570bfa;hp=4be1c3ec0dbde87c1b7ae9b380ea496891df82f2;hpb=830d494c7fbbd0591e185378d8cf8085673e6b8c;p=calu.git

diff --git a/cpu/src/decode_stage.vhd b/cpu/src/decode_stage.vhd
index 4be1c3e..620a2cc 100644
--- a/cpu/src/decode_stage.vhd
+++ b/cpu/src/decode_stage.vhd
@@ -2,19 +2,42 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
+use work.core_pkg.all;
+use work.common_pkg.all;
+
+
 entity decode_stage is
 
 	generic	(
 			-- active reset value
 			RESET_VALUE : std_logic;
 			-- active logic value
-			LOGIC_ACT : std_logic;
+			LOGIC_ACT : std_logic
 			
 			);
 	port(
 		--System inputs
 			clk : in std_logic;
 			reset : in std_logic;
+
+		--Data inputs
+			instruction : in instruction_word_t;
+			prog_cnt : in instruction_addr_t;
+			reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+			reg_wr_data : in gp_register_t;
+			reg_we : in std_logic;
+			nop : in std_logic;
+
+		--Data outputs
+--			reg1_rd_data : out gp_register_t;
+--			reg2_rd_data : out gp_register_t;
+			branch_prediction_res : out instruction_addr_t;
+			branch_prediction_bit : out std_logic;
+
+			to_next_stage : out dec_op
+			
 		);
 		
 end decode_stage;
+
+