X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fcore_top_s3e.vhd;h=30c2dd1915ce4d1a93aee55bb0ad0735c1eb1278;hb=HEAD;hp=eb1082322f202fe6bcd2bdb70d448bf7bac8d277;hpb=8558b10449023bd73fafd703e7c3cddff012cb8e;p=calu.git diff --git a/cpu/src/core_top_s3e.vhd b/cpu/src/core_top_s3e.vhd index eb10823..30c2dd1 100644 --- a/cpu/src/core_top_s3e.vhd +++ b/cpu/src/core_top_s3e.vhd @@ -1,3 +1,24 @@ +-- `Deep Thought', a softcore CPU implemented on a FPGA +-- +-- Copyright (C) 2010 Markus Hofstaetter +-- Copyright (C) 2010 Martin Perner +-- Copyright (C) 2010 Stefan Rebernig +-- Copyright (C) 2010 Manfred Schwarz +-- Copyright (C) 2010 Bernhard Urban +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . + library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; @@ -11,6 +32,7 @@ entity core_top is port( --System input pins sys_res : in std_logic; + soft_res : in std_logic; sys_clk : in std_logic; -- result : out gp_register_t; -- reg_wr_data : out gp_register_t @@ -18,6 +40,7 @@ entity core_top is bus_tx : out std_logic; bus_rx : in std_logic; led1 : out std_logic; + led2 : out std_logic; sseg0 : out std_logic_vector(0 to 6); sseg1 : out std_logic_vector(0 to 6); @@ -64,8 +87,9 @@ architecture behav of core_top is signal gpm_out_pin : gp_register_t; signal nop_pin : std_logic; - signal sync : std_logic_vector(1 to SYNC_STAGES); - signal sys_res_n : std_logic; + signal sync, sync2 : std_logic_vector(1 to SYNC_STAGES); + signal sys_res_n, soft_res_n : std_logic; + signal xilinxfail : std_logic; signal int_req : interrupt_t; @@ -86,7 +110,7 @@ begin --System inputs clk => sys_clk, --: in std_logic; reset => sys_res_n, --: in std_logic; - + s_reset => soft_res_n, --Data inputs jump_result => jump_result_pin, --: in instruction_addr_t; prediction_result => prediction_result_pin, --: in instruction_addr_t; @@ -99,7 +123,8 @@ begin im_data => im_data, --Data outputs instruction => instruction_pin, --: out instruction_word_t - prog_cnt => prog_cnt_pin + prog_cnt => prog_cnt_pin, + led2 => led2 ); decode_st : decode_stage @@ -113,7 +138,7 @@ begin port map ( --System inputs clk => sys_clk, --: in std_logic; - reset => sys_res_n, -- : in std_logic; + reset => xilinxfail, -- : in std_logic; --Data inputs instruction => instruction_pin, --: in instruction_word_t; @@ -131,7 +156,7 @@ begin exec_st : execute_stage generic map('0') - port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin, + port map(sys_clk, xilinxfail,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin, data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin); @@ -155,13 +180,14 @@ begin -- writeback_st : writeback_stage - generic map('0', '1', "s3e") - port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, + generic map('0', '1', "s3e", 434) + port map(sys_clk, xilinxfail, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, -- instruction memory program port :D new_im_data, im_addr, im_data, - sseg0, sseg1, sseg2, sseg3, int_req); + -- sseg0, sseg1, sseg2, sseg3, + int_req); syn: process(sys_clk, sys_res) @@ -183,6 +209,7 @@ begin -- vers.byte_s <= '0'; sync <= (others => '0'); + sync2 <= (others => '0'); elsif rising_edge(sys_clk) then led1 <= '1'; @@ -191,12 +218,17 @@ begin for i in 2 to SYNC_STAGES loop sync(i) <= sync(i - 1); end loop; - + sync2(1) <= not soft_res; + for i in 2 to SYNC_STAGES loop + sync2(i) <= sync2(i - 1); + end loop; end if; end process; sys_res_n <= sync(SYNC_STAGES); +soft_res_n <= sync2(SYNC_STAGES); +xilinxfail <= sys_res_n and soft_res_n; --init : process(all)