X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fcore_top.vhd;h=f7e0a75c1a4c9988e29ecb8b9efbee829502fa29;hb=1968f329b10681b760faec9369aa893cd2af8d44;hp=eafb605135bf9a5dcee5c06f88cfc2bb21e6b563;hpb=e42af2345f9574b9c54ac4deb799670581c8680d;p=calu.git diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd index eafb605..f7e0a75 100644 --- a/cpu/src/core_top.vhd +++ b/cpu/src/core_top.vhd @@ -1,3 +1,24 @@ +-- `Deep Thought', a softcore CPU implemented on a FPGA +-- +-- Copyright (C) 2010 Markus Hofstaetter +-- Copyright (C) 2010 Martin Perner +-- Copyright (C) 2010 Stefan Rebernig +-- Copyright (C) 2010 Manfred Schwarz +-- Copyright (C) 2010 Bernhard Urban +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . + library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; @@ -11,17 +32,19 @@ entity core_top is port( --System input pins sys_res : in std_logic; - sys_clk : in std_logic; + soft_res : in std_logic; + sys_clk_in : in std_logic; -- result : out gp_register_t; -- reg_wr_data : out gp_register_t -- uart bus_tx : out std_logic; bus_rx : in std_logic; + led2 : out std_logic - sseg0 : out std_logic_vector(0 to 6); - sseg1 : out std_logic_vector(0 to 6); - sseg2 : out std_logic_vector(0 to 6); - sseg3 : out std_logic_vector(0 to 6) + --sseg0 : out std_logic_vector(0 to 6); + --sseg1 : out std_logic_vector(0 to 6); + --sseg2 : out std_logic_vector(0 to 6); + --sseg3 : out std_logic_vector(0 to 6) ); end core_top; @@ -31,6 +54,8 @@ architecture behav of core_top is constant SYNC_STAGES : integer := 2; constant RESET_VALUE : std_logic := '0'; + signal sys_clk : std_logic; + signal jump_result : instruction_addr_t; signal jump_result_pin : instruction_addr_t; signal prediction_result_pin : instruction_addr_t; @@ -63,12 +88,32 @@ architecture behav of core_top is signal gpm_out_pin : gp_register_t; signal nop_pin : std_logic; - signal sync : std_logic_vector(1 to SYNC_STAGES); - signal sys_res_n : std_logic; + signal sync, sync2 : std_logic_vector(1 to SYNC_STAGES); + signal sys_res_n, soft_res_n : std_logic; + + signal int_req : interrupt_t; + + signal new_im_data : std_logic; + signal im_addr, im_data : gp_register_t; signal vers, vers_nxt : exec2wb_rec; + + + component pll + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC + ); + end component; begin + pll_inst : pll PORT MAP ( + inclk0 => sys_clk_in, + c0 => sys_clk + ); + + fetch_st : fetch_stage generic map ( @@ -80,16 +125,21 @@ begin --System inputs clk => sys_clk, --: in std_logic; reset => sys_res_n, --: in std_logic; - + s_reset => soft_res_n, --Data inputs jump_result => jump_result_pin, --: in instruction_addr_t; prediction_result => prediction_result_pin, --: in instruction_addr_t; branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic; alu_jump_bit => alu_jump_bit_pin, --: in std_logic; - + int_req => int_req, + -- instruction memory program port :D + new_im_data_in => new_im_data, + im_addr => im_addr, + im_data => im_data, --Data outputs instruction => instruction_pin, --: out instruction_word_t - prog_cnt => prog_cnt_pin + prog_cnt => prog_cnt_pin, + led2 => led2 ); decode_st : decode_stage @@ -103,7 +153,7 @@ begin port map ( --System inputs clk => sys_clk, --: in std_logic; - reset => sys_res_n, -- : in std_logic; + reset => sys_res_n and soft_res_n, -- : in std_logic; --Data inputs instruction => instruction_pin, --: in instruction_word_t; @@ -121,7 +171,7 @@ begin exec_st : execute_stage generic map('0') - port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin, + port map(sys_clk, sys_res_n and soft_res_n, to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin, data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin); @@ -145,17 +195,21 @@ begin -- writeback_st : writeback_stage - generic map('0', '1') - port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, + generic map('0', '1', "altera", 5208) + port map(sys_clk, sys_res_n and soft_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s, - reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, sseg0, sseg1, sseg2, sseg3); + reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, + -- instruction memory program port :D + new_im_data, im_addr, im_data, + --sseg0, sseg1, sseg2, sseg3, + int_req); -syn: process(sys_clk, sys_res) +syn: process(sys_clk, sys_res, soft_res) begin - if sys_res = '0' then + if sys_res = '1' then -- vers.result <= (others => '0'); -- vers.result_addr <= (others => '0'); -- vers.address <= (others => '0'); @@ -169,19 +223,25 @@ begin -- vers.byte_s <= '0'; sync <= (others => '0'); + sync2 <= (others => '0'); elsif rising_edge(sys_clk) then -- vers <= vers_nxt; - sync(1) <= sys_res; + sync(1) <= not sys_res; for i in 2 to SYNC_STAGES loop sync(i) <= sync(i - 1); end loop; - + sync2(1) <= not soft_res; + for i in 2 to SYNC_STAGES loop + sync2(i) <= sync2(i - 1); + end loop; end if; + end process; sys_res_n <= sync(SYNC_STAGES); +soft_res_n <= sync2(SYNC_STAGES); --init : process(all)