X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fcore_top.vhd;h=a8d3bde57bfbc280729be3cd777bf3733779c9bf;hb=a37bfd1075f405931099ba5cc347b3954855675e;hp=13d826353a37e25de0c3d57c7922b4984fd80bee;hpb=a70afaae294cdb93b51ca938ddf18e2ce88f0451;p=calu.git

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index 13d8263..a8d3bde 100644
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -11,18 +11,19 @@ entity core_top is
 	port(
 		--System input pins
 		   sys_res : in std_logic;
-			sys_clk : in std_logic;
+			soft_res : in std_logic;
+			sys_clk_in : in std_logic;
 --			result : out gp_register_t;
 --			reg_wr_data : out gp_register_t
 		  -- uart
 			bus_tx : out std_logic;
 			bus_rx : in std_logic;
-			led2 : out std_logic;
+			led2 : out std_logic
 			
-			sseg0 : out std_logic_vector(0 to 6);
-			sseg1 : out std_logic_vector(0 to 6);
-			sseg2 : out std_logic_vector(0 to 6);
-			sseg3 : out std_logic_vector(0 to 6)
+			--sseg0 : out std_logic_vector(0 to 6);
+			--sseg1 : out std_logic_vector(0 to 6);
+			--sseg2 : out std_logic_vector(0 to 6);
+			--sseg3 : out std_logic_vector(0 to 6)
 		);
 
 end core_top;
@@ -32,6 +33,8 @@ architecture behav of core_top is
 		constant SYNC_STAGES : integer := 2;
 		constant RESET_VALUE : std_logic := '0';
 
+		signal sys_clk : std_logic;
+
 		signal jump_result : instruction_addr_t;
 		signal jump_result_pin : instruction_addr_t;
 		signal prediction_result_pin : instruction_addr_t;
@@ -64,8 +67,8 @@ architecture behav of core_top is
 		 signal gpm_out_pin : gp_register_t;
 		 signal nop_pin : std_logic;
 		 
-		 signal sync : std_logic_vector(1 to SYNC_STAGES);
-		 signal sys_res_n : std_logic;
+		 signal sync, sync2 : std_logic_vector(1 to SYNC_STAGES);
+		 signal sys_res_n, soft_res_n : std_logic;
 
 		 signal int_req : interrupt_t;
 
@@ -73,8 +76,23 @@ architecture behav of core_top is
 		 signal im_addr, im_data : gp_register_t;
 		 
 		 signal vers, vers_nxt : exec2wb_rec;
+
+
+	component pll
+		PORT
+		(
+			inclk0 : IN STD_LOGIC  := '0';
+			c0	    : OUT STD_LOGIC
+		);
+	end component;
 begin
 
+	pll_inst : pll PORT MAP (
+		inclk0 => sys_clk_in,
+		c0     => sys_clk
+	);
+
+
 	fetch_st : fetch_stage
 		generic map (
 	
@@ -86,7 +104,7 @@ begin
 		--System inputs
 			clk => sys_clk, --: in std_logic;
 			reset => sys_res_n, --: in std_logic;
-		
+			s_reset => soft_res_n,
 		--Data inputs
 			jump_result => jump_result_pin, --: in instruction_addr_t;
 			prediction_result => prediction_result_pin, --: in instruction_addr_t;
@@ -114,7 +132,7 @@ begin
 		port map (
 		--System inputs
 			clk => sys_clk, --: in std_logic;
-			reset => sys_res_n, -- : in std_logic;
+			reset => sys_res_n and soft_res_n, -- : in std_logic;
 
 		--Data inputs
 			instruction => instruction_pin, --: in instruction_word_t;
@@ -132,7 +150,7 @@ begin
 
           exec_st : execute_stage
                 generic map('0')
-                port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+                port map(sys_clk, sys_res_n and soft_res_n, to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
 
@@ -156,16 +174,17 @@ begin
 --
 
 			writeback_st : writeback_stage
-                generic map('0', '1', "altera")
-                port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
+                generic map('0', '1', "altera", 2083)
+                port map(sys_clk, sys_res_n and soft_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
 				-- instruction memory program port :D
 				new_im_data, im_addr, im_data,
-				sseg0, sseg1, sseg2, sseg3, int_req);
+				--sseg0, sseg1, sseg2, sseg3,
+				 int_req);
 
 
-syn: process(sys_clk, sys_res)
+syn: process(sys_clk, sys_res, soft_res)
 
 begin
 
@@ -183,6 +202,7 @@ begin
 --			vers.byte_s <= '0';
 	
 		sync <= (others => '0');
+		sync2 <= (others => '0');
 	
 	elsif rising_edge(sys_clk) then
 --		vers <= vers_nxt;
@@ -190,12 +210,17 @@ begin
 			for i in 2 to SYNC_STAGES loop
 				sync(i) <= sync(i - 1);
 			end loop;
-				
+			sync2(1) <= not soft_res;
+			for i in 2 to SYNC_STAGES loop
+				sync2(i) <= sync2(i - 1);
+			end loop;
 	end if;
+
 	
 end process;
 
 sys_res_n <= sync(SYNC_STAGES);
+soft_res_n <= sync2(SYNC_STAGES);
 	
 --init : process(all)