X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fcore_top.vhd;h=531ccd1b43f9b6027076d9aaedbb58b5ff699ed7;hb=0a7c3ba7339003e4918db8ca5c2495c0b9abf941;hp=1002989d03e2fcbca282ee82d7e221219f24bc14;hpb=e015478bf1add42f6c2e49652360b3fae08d94f5;p=calu.git diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd index 1002989..531ccd1 100644 --- a/cpu/src/core_top.vhd +++ b/cpu/src/core_top.vhd @@ -10,18 +10,32 @@ entity core_top is port( --System input pins - sys_clk : in std_logic; - sys_res : in std_logic; + sys_res : in std_logic; + soft_res : in std_logic; + sys_clk_in : in std_logic; -- result : out gp_register_t; - jump_result : out instruction_addr_t -- reg_wr_data : out gp_register_t + -- uart + bus_tx : out std_logic; + bus_rx : in std_logic; + led2 : out std_logic + --sseg0 : out std_logic_vector(0 to 6); + --sseg1 : out std_logic_vector(0 to 6); + --sseg2 : out std_logic_vector(0 to 6); + --sseg3 : out std_logic_vector(0 to 6) ); end core_top; architecture behav of core_top is + constant SYNC_STAGES : integer := 2; + constant RESET_VALUE : std_logic := '0'; + + signal sys_clk : std_logic; + + signal jump_result : instruction_addr_t; signal jump_result_pin : instruction_addr_t; signal prediction_result_pin : instruction_addr_t; signal branch_prediction_bit_pin : std_logic; @@ -52,10 +66,33 @@ architecture behav of core_top is signal gpm_in_pin : extmod_rec; signal gpm_out_pin : gp_register_t; signal nop_pin : std_logic; + + signal sync, sync2 : std_logic_vector(1 to SYNC_STAGES); + signal sys_res_n, soft_res_n : std_logic; + + signal int_req : interrupt_t; + signal new_im_data : std_logic; + signal im_addr, im_data : gp_register_t; + + signal vers, vers_nxt : exec2wb_rec; + + component pll + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC + ); + end component; begin + pll_inst : pll PORT MAP ( + inclk0 => sys_clk_in, + c0 => sys_clk + ); + + fetch_st : fetch_stage generic map ( @@ -66,17 +103,22 @@ begin port map ( --System inputs clk => sys_clk, --: in std_logic; - reset => sys_res, --: in std_logic; - + reset => sys_res_n, --: in std_logic; + s_reset => soft_res_n, --Data inputs jump_result => jump_result_pin, --: in instruction_addr_t; prediction_result => prediction_result_pin, --: in instruction_addr_t; branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic; alu_jump_bit => alu_jump_bit_pin, --: in std_logic; - + int_req => int_req, + -- instruction memory program port :D + new_im_data_in => new_im_data, + im_addr => im_addr, + im_data => im_data, --Data outputs instruction => instruction_pin, --: out instruction_word_t - prog_cnt => prog_cnt_pin + prog_cnt => prog_cnt_pin, + led2 => led2 ); decode_st : decode_stage @@ -90,7 +132,7 @@ begin port map ( --System inputs clk => sys_clk, --: in std_logic; - reset => sys_res, -- : in std_logic; + reset => sys_res_n and soft_res_n, -- : in std_logic; --Data inputs instruction => instruction_pin, --: in instruction_word_t; @@ -108,19 +150,78 @@ begin exec_st : execute_stage generic map('0') - port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin, + port map(sys_clk, sys_res_n and soft_res_n, to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin, data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin); - writeback_st : writeback_stage - generic map('0', '1') - port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, - wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin, - reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin); + vers_nxt.result <= result_pin; + vers_nxt.result_addr <= result_addr_pin; + vers_nxt.address <= addr_pin; + vers_nxt.ram_data <= data_pin; + vers_nxt.alu_jmp <= alu_jump_pin; + vers_nxt.br_pred <= brpr_pin; + vers_nxt.write_en <= wr_en_pin; + vers_nxt.dmem_en <= dmem_pin; + vers_nxt.dmem_write_en <= dmem_wr_en_pin; + vers_nxt.hword <= hword_pin; + vers_nxt.byte_s <= byte_s_pin; + +-- writeback_st : writeback_stage +-- generic map('0', '1') +-- port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, +-- wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin, +-- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3); +-- + + writeback_st : writeback_stage + generic map('0', '1', "altera", 5208) + port map(sys_clk, sys_res_n and soft_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, + vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s, + reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, + -- instruction memory program port :D + new_im_data, im_addr, im_data, + --sseg0, sseg1, sseg2, sseg3, + int_req); + + +syn: process(sys_clk, sys_res, soft_res) +begin + if sys_res = '1' then +-- vers.result <= (others => '0'); +-- vers.result_addr <= (others => '0'); +-- vers.address <= (others => '0'); +-- vers.ram_data <= (others => '0'); +-- vers.alu_jmp <= '0'; +-- vers.br_pred <= '0'; +-- vers.write_en <= '0'; +-- vers.dmem_en <= '0'; +-- vers.dmem_write_en <= '0'; +-- vers.hword <= '0'; +-- vers.byte_s <= '0'; + + sync <= (others => '0'); + sync2 <= (others => '0'); + + elsif rising_edge(sys_clk) then +-- vers <= vers_nxt; + sync(1) <= not sys_res; + for i in 2 to SYNC_STAGES loop + sync(i) <= sync(i - 1); + end loop; + sync2(1) <= not soft_res; + for i in 2 to SYNC_STAGES loop + sync2(i) <= sync2(i - 1); + end loop; + end if; - + +end process; + +sys_res_n <= sync(SYNC_STAGES); +soft_res_n <= sync2(SYNC_STAGES); + --init : process(all) --begin @@ -136,6 +237,8 @@ begin nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin); jump_result <= prog_cnt_pin; --jump_result_pin; +-- sys_res <= '1'; -- reg_wr_data <= reg_wr_data_pin; + end behav;