X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fcore_top.vhd;fp=cpu%2Fsrc%2Fcore_top.vhd;h=9e0c9967426cb2c39b1c81a74f62ab8be9175553;hb=4d230c21bb8c9c23c3dd3349f8736b84987eab0d;hp=1002989d03e2fcbca282ee82d7e221219f24bc14;hpb=2d98d2f7b3eaa3afc1cc264725b2596184f1e6e3;p=calu.git

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index 1002989..9e0c996 100644
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -11,17 +11,18 @@ entity core_top is
 	port(
 		--System input pins
 			sys_clk : in std_logic;
-			sys_res : in std_logic;
 --			result : out gp_register_t;
-			jump_result : out instruction_addr_t
 --			reg_wr_data : out gp_register_t
-			
+		  -- uart
+			bus_tx : out std_logic
 		);
 
 end core_top;
 
 architecture behav of core_top is
 
+		signal jump_result : instruction_addr_t;
+		signal sys_res : std_logic;
 		signal jump_result_pin : instruction_addr_t;
 		signal prediction_result_pin : instruction_addr_t;
 		signal branch_prediction_bit_pin : std_logic;
@@ -115,7 +116,7 @@ begin
                 generic map('0', '1')
                 port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx);
 
 
 
@@ -136,6 +137,7 @@ begin
 	nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
 
 	jump_result <= prog_cnt_pin; --jump_result_pin;
+	sys_res <= '1';
 
 --	reg_wr_data <= reg_wr_data_pin;
 end behav;