X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fcore_pkg.vhd;h=bd13a9c1ac4445c9a12a1c574215f47478afdbf5;hb=a37bfd1075f405931099ba5cc347b3954855675e;hp=afd50b666d4153702c1f1c91d54257f3606a4a8c;hpb=64ef7ca2830116409f4c23802a202ab4b1ce5ec8;p=calu.git

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index afd50b6..bd13a9c 100644
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -20,16 +20,23 @@ package core_pkg is
 		--System inputs
 			clk : in std_logic;
 			reset : in std_logic;
+			s_reset : in std_logic;
 		
 		--Data inputs
 			jump_result : in instruction_addr_t;
 			prediction_result : in instruction_addr_t;
 			branch_prediction_bit : in std_logic;
 			alu_jump_bit : in std_logic;
+			int_req : in interrupt_t;
+			new_im_data_in : in std_logic;
+			im_addr : in gp_register_t;
+			im_data : in gp_register_t;
 
 		--Data outputs
 			instruction : out instruction_word_t;
-			prog_cnt : out instruction_addr_t
+			prog_cnt : out instruction_addr_t;
+		-- debug
+			led2 : out std_logic
 		);
 	end component fetch_stage;
 
@@ -59,7 +66,7 @@ package core_pkg is
 		--Data outputs
 --			reg1_rd_data : out gp_register_t;
 --			reg2_rd_data : out gp_register_t;
-			branch_prediction_res : out instruction_word_t;
+			branch_prediction_res : out instruction_addr_t;
 			branch_prediction_bit : out std_logic;
 
 			to_next_stage : out dec_op
@@ -119,8 +126,9 @@ package core_pkg is
 			-- active reset value
 			RESET_VALUE : std_logic;
 			-- active logic value
-			LOGIC_ACT : std_logic
-			
+			LOGIC_ACT : std_logic;
+			FPGATYPE : string;
+			CLK_BAUD : integer
 			);
 	port(
 		--System inputs
@@ -147,11 +155,17 @@ package core_pkg is
 			-- same here
 			bus_tx : out std_logic;
 			bus_rx : in std_logic;
+			new_im_data_out : out std_logic;
+			im_addr : out gp_register_t;
+			im_data : out gp_register_t;
 			
-			sseg0 : out std_logic_vector(0 to 6);
-			sseg1 : out std_logic_vector(0 to 6);
-			sseg2 : out std_logic_vector(0 to 6);
-			sseg3 : out std_logic_vector(0 to 6)
+			--sseg0 : out std_logic_vector(0 to 6);
+			--sseg1 : out std_logic_vector(0 to 6);
+			--sseg2 : out std_logic_vector(0 to 6);
+			--sseg3 : out std_logic_vector(0 to 6);
+
+			int_req : out interrupt_t
+
 		);
 	end component writeback_stage;