X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fcore_pkg.vhd;h=9ca6bb5de5bc24774e6df6f34c422b7fde6350f4;hb=1968f329b10681b760faec9369aa893cd2af8d44;hp=23403444070c499105e7969bddd1c2caf4c92ead;hpb=c22560759ba6cbf74fc32fc5b20609156942ee0f;p=calu.git

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index 2340344..9ca6bb5 100644
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 
 use IEEE.std_logic_1164.all;
@@ -20,16 +41,23 @@ package core_pkg is
 		--System inputs
 			clk : in std_logic;
 			reset : in std_logic;
+			s_reset : in std_logic;
 		
 		--Data inputs
 			jump_result : in instruction_addr_t;
 			prediction_result : in instruction_addr_t;
 			branch_prediction_bit : in std_logic;
 			alu_jump_bit : in std_logic;
+			int_req : in interrupt_t;
+			new_im_data_in : in std_logic;
+			im_addr : in gp_register_t;
+			im_data : in gp_register_t;
 
 		--Data outputs
 			instruction : out instruction_word_t;
-			prog_cnt : out instruction_addr_t
+			prog_cnt : out instruction_addr_t;
+		-- debug
+			led2 : out std_logic
 		);
 	end component fetch_stage;
 
@@ -59,7 +87,7 @@ package core_pkg is
 		--Data outputs
 --			reg1_rd_data : out gp_register_t;
 --			reg2_rd_data : out gp_register_t;
-			branch_prediction_res : out instruction_word_t;
+			branch_prediction_res : out instruction_addr_t;
 			branch_prediction_bit : out std_logic;
 
 			to_next_stage : out dec_op
@@ -119,8 +147,9 @@ package core_pkg is
 			-- active reset value
 			RESET_VALUE : std_logic;
 			-- active logic value
-			LOGIC_ACT : std_logic
-			
+			LOGIC_ACT : std_logic;
+			FPGATYPE : string;
+			CLK_BAUD : integer
 			);
 	port(
 		--System inputs
@@ -143,7 +172,21 @@ package core_pkg is
 			reg_we : out std_logic;
 			reg_addr : out gp_addr_t;
 			jump_addr : out instruction_addr_t;
-			jump : out std_logic
+			jump : out std_logic;
+			-- same here
+			bus_tx : out std_logic;
+			bus_rx : in std_logic;
+			new_im_data_out : out std_logic;
+			im_addr : out gp_register_t;
+			im_data : out gp_register_t;
+			
+			--sseg0 : out std_logic_vector(0 to 6);
+			--sseg1 : out std_logic_vector(0 to 6);
+			--sseg2 : out std_logic_vector(0 to 6);
+			--sseg3 : out std_logic_vector(0 to 6);
+
+			int_req : out interrupt_t
+
 		);
 	end component writeback_stage;