X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Fcore_pkg.vhd;h=9731f37592de2f49322534d87c8968b0f6da25a3;hb=ea11b8a1f00f62aed7584f257f0a8a90e982a707;hp=3f916fb3d3701906df26a56e0aaafac3ba85497f;hpb=bade9b27a9aa3b27e13aff54dd083bd5a4baa3e1;p=calu.git

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index 3f916fb..9731f37 100644
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -4,6 +4,7 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
+use work.extension_pkg.all;
 
 package core_pkg is
 	
@@ -19,16 +20,23 @@ package core_pkg is
 		--System inputs
 			clk : in std_logic;
 			reset : in std_logic;
-
+			s_reset : in std_logic;
+		
 		--Data inputs
 			jump_result : in instruction_addr_t;
 			prediction_result : in instruction_addr_t;
 			branch_prediction_bit : in std_logic;
 			alu_jump_bit : in std_logic;
+			int_req : in interrupt_t;
+			new_im_data_in : in std_logic;
+			im_addr : in gp_register_t;
+			im_data : in gp_register_t;
 
 		--Data outputs
-			instruction : out instruction_word_t
-
+			instruction : out instruction_word_t;
+			prog_cnt : out instruction_addr_t;
+		-- debug
+			led2 : out std_logic
 		);
 	end component fetch_stage;
 
@@ -49,15 +57,18 @@ package core_pkg is
 
 		--Data inputs
 			instruction : in instruction_word_t;
+			prog_cnt : in instruction_addr_t;
 			reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
 			reg_wr_data : in gp_register_t;
 			reg_we : in std_logic;
+			nop : in std_logic;
 
 		--Data outputs
 --			reg1_rd_data : out gp_register_t;
 --			reg2_rd_data : out gp_register_t;
 			branch_prediction_res : out instruction_word_t;
 			branch_prediction_bit : out std_logic;
+
 			to_next_stage : out dec_op
 		);
 	end component decode_stage;
@@ -74,17 +85,37 @@ package core_pkg is
 	end component decoder;
 
 	component execute_stage is
+	
 	generic	(
 			-- active reset value
-			RESET_VALUE : std_logic;
+			RESET_VALUE : std_logic
 			-- active logic value
-			LOGIC_ACT : std_logic
+			--LOGIC_ACT : std_logic;
 			
 			);
 	port(
 		--System inputs
 			clk : in std_logic;
-			reset : in std_logic
+			reset : in std_logic;
+                        dec_instr : in dec_op;
+			regfile_val : in gp_register_t;
+			reg_we : in std_logic;
+			reg_addr : in gp_addr_t;
+			ext_reg  : in extmod_rec;
+            --System output
+            result : out gp_register_t;--reg
+            result_addr : out gp_addr_t;--reg
+            addr : out word_t; --memaddr
+            data : out gp_register_t; --mem data --ureg
+            alu_jump : out std_logic;--reg
+            brpr  : out std_logic;  --reg
+            wr_en : out std_logic;--regop --reg
+            dmem  : out std_logic;--memop
+            dmem_write_en : out std_logic;
+            hword  : out std_logic;
+            byte_s : out std_logic;
+				
+			ext_data_out : out gp_register_t
 		);
 	end component execute_stage;
 
@@ -95,13 +126,46 @@ package core_pkg is
 			-- active reset value
 			RESET_VALUE : std_logic;
 			-- active logic value
-			LOGIC_ACT : std_logic
-			
+			LOGIC_ACT : std_logic;
+			FPGATYPE : string;
+			CLK_BAUD : integer
 			);
 	port(
 		--System inputs
 			clk : in std_logic;
-			reset : in std_logic
+			reset : in std_logic;
+
+			result : in gp_register_t;	--reg  (alu result or jumpaddr)
+			result_addr : in gp_addr_t;	--reg
+			address : in word_t;		--ureg 
+			ram_data : in word_t;		--ureg
+			alu_jmp : in std_logic;		--reg
+			br_pred : in std_logic;		--reg
+			write_en : in std_logic;	--reg  (register file)
+			dmem_en : in std_logic;		--ureg (jump addr in mem or in address)
+			dmem_write_en : in std_logic;	--ureg
+			hword : in std_logic;		--ureg
+			byte_s : in std_logic;		--ureg  
+
+			regfile_val : out gp_register_t;
+			reg_we : out std_logic;
+			reg_addr : out gp_addr_t;
+			jump_addr : out instruction_addr_t;
+			jump : out std_logic;
+			-- same here
+			bus_tx : out std_logic;
+			bus_rx : in std_logic;
+			new_im_data_out : out std_logic;
+			im_addr : out gp_register_t;
+			im_data : out gp_register_t;
+			
+			sseg0 : out std_logic_vector(0 to 6);
+			sseg1 : out std_logic_vector(0 to 6);
+			sseg2 : out std_logic_vector(0 to 6);
+			sseg3 : out std_logic_vector(0 to 6);
+
+			int_req : out interrupt_t
+
 		);
 	end component writeback_stage;