X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Falu_b.vhd;h=c170ce6351bee19ccb8ed4b7e2b8a2c344188b6e;hb=afedb369e2082b0e887941faa4326f3c11eff20d;hp=c9e832e9c9ed321c37360beea36476d66e57ad04;hpb=2f1bd33623f23cd0cafd3cd2e5d4d1f620d9a2be;p=calu.git

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index c9e832e..c170ce6 100755
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -75,7 +75,11 @@ begin
 	paddr <= (others =>'0');
 	
 	result_v.result := add_result.result;
-	prog_cnt_nxt := std_logic_vector(unsigned(prog_cnt)+1);
+	if (op_detail(DIRECT_JUMP_OPT) = '0') then
+		prog_cnt_nxt := std_logic_vector(unsigned(prog_cnt)+1);
+	else
+		prog_cnt_nxt := prog_cnt;
+	end if;
 	case cond is
 	when COND_NZERO =>
 		cond_met := not(alu_state.status.zero);
@@ -118,23 +122,40 @@ begin
 	case op_group is
 	when ADDSUB_OP =>
 		result_v := add_result;
+		addr(DATA_ADDR_WIDTH + 2) <= '0';
 	when AND_OP =>
 		result_v := and_result;
+		addr(DATA_ADDR_WIDTH + 2) <= '0';
 	when OR_OP =>
 		result_v := or_result;
+		addr(DATA_ADDR_WIDTH + 2) <= '0';
 	when XOR_OP =>
 		result_v := xor_result;
+		addr(DATA_ADDR_WIDTH + 2) <= '0';
 	when SHIFT_OP =>
 		result_v := shift_result;
+		addr(DATA_ADDR_WIDTH + 2) <= '0';
    when LDST_OP =>
                 res_prod := '0';
                 mem_op := '1';
 		--right_o <= displacement;
 		addr <= std_logic_vector(unsigned(left_operand)+unsigned(displacement));
                 if op_detail(IMM_OPT) = '1' then
-                        result_v.result := right_operand;
+					 
+								result_v.result := right_operand;
+					 
+								if (op_detail(LDI_REPLACE_OPT) = '0') then
+									result_v.result := left_operand;
+									if (op_detail(LOW_HIGH_OPT) = '1') then
+										result_v.result(31 downto 16) := right_operand(31 downto 16);
+									else
+										result_v.result(15 downto 0) := right_operand(15 downto 0);
+									end if;
+								end if;
+
                         res_prod := '1';
                         mem_op := '0';
+								addr(DATA_ADDR_WIDTH + 2) <= '0';
                 end if;
                 if op_detail(ST_OPT) = '1' then
                         mem_en := '1';
@@ -173,7 +194,7 @@ begin
 			pinc_v := '1';
 			res_prod := '0';
 			addr <= pval_nxt;
-			data <= left_o;
+			data <= left_operand;
 		else
 			addr <= std_logic_vector(unsigned(pval_nxt)-4);
 		end if;