X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Falu_b.vhd;h=696e0f798fb647394689a9e147b3e0522f0a3aa4;hb=d1e680464f7b7147dc4b435a27973621fd69f065;hp=8399d6087e835d11d1375fc5a43e4c7d5bf10c27;hpb=8173b5fa1ed9ea2a213f8f23ee9ed92869203884;p=calu.git

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index 8399d60..696e0f7 100755
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -21,7 +21,7 @@ architecture behaviour of alu is
 	);			
 	end component exec_op;
 	
-	signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;
+	signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;
         signal left, right : gp_register_t;
 	
 begin
@@ -41,28 +41,29 @@ begin
 	shift_inst : entity work.exec_op(shift_op)
 	port map(clk,reset,left, right, op_detail, alu_state, shift_result);
 
-calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)
+calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr)
 	variable result_v : alu_result_rec;
 	variable res_prod : std_logic;
 	variable cond_met : std_logic;
-	variable mem_en : std_logic;
-        variable mem_op : std_logic;
-	variable alu_jmp : std_logic;
+	variable mem_en : std_logic;
+        variable mem_op : std_logic;
+	variable alu_jump : std_logic;
+	variable nop     : std_logic;
 begin
 	result_v := alu_state;
 	
 	res_prod := '1';
-	mem_en := '0';
-        mem_op := '0';
+	mem_en := '0';
+        mem_op := '0';
 	alu_jump := '0';
-  
-        left <= left_operand;
-        right <= right_operand;
-
-        addr <= add_result.result;
+  
+        left <= left_operand;
+        right <= right_operand;
+
+        addr <= add_result.result;
         data <= right_operand;
-	
-	result_v.result := add_result.result;
+	
+	result_v.result := add_result.result;
 
 	case cond is
 	when COND_NZERO =>
@@ -99,8 +100,9 @@ begin
 		cond_met := '0';
 	when others => null;
 	end case;
-	
-	cond_met := cond_met and (alu_state.alu_jmp xnor alu_state.brpr);
+	
+	nop := (alu_state.alu_jump xnor alu_state.brpr);
+	cond_met := cond_met and nop;
 
 	case op_group is
 	when ADDSUB_OP =>
@@ -112,24 +114,24 @@ begin
 	when XOR_OP =>
 		result_v := xor_result;
 	when SHIFT_OP =>
-		result_v := shift_result;
-        when LDST_OP =>
-                res_prod := '0';
-                mem_op := '1';
-                if op_detail(IMM_OPT) = '1' then
-                        result_v.result := right_operand;
-                        res_prod := '1';
-                        mem_op := '0';
-                end if;
-                if op_detail(ST_OPT) = '1' then
-                        right <= displacement;
-                        mem_en := '1';
-                end if;
-	when JMP_OP =>
-		if op_detail(JMP_REG_OPT) = '0' then
-			left <= prog_cnt;
-		end if;
-		result_v.alu_jmp := '1';
+		result_v := shift_result;
+        when LDST_OP =>
+                res_prod := '0';
+                mem_op := '1';
+                if op_detail(IMM_OPT) = '1' then
+                        result_v.result := right_operand;
+                        res_prod := '1';
+                        mem_op := '0';
+                end if;
+                if op_detail(ST_OPT) = '1' then
+                        right <= displacement;
+                        mem_en := '1';
+                end if;
+	when JMP_OP =>
+		if op_detail(JMP_REG_OPT) = '0' then
+			left <= prog_cnt;
+		end if;
+		alu_jump := '1';
 	when JMP_ST_OP => null;
 	end case;
 	
@@ -146,10 +148,17 @@ begin
 	end if;
 	
 	result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;
-	result_v.mem_en := mem_en and cond_met;
-        result_v.mem_op := mem_op and cond_met;
-	result_v.alu_jmp := alu_jmp and cond_met;
+	result_v.mem_en := mem_en and cond_met;
+        result_v.mem_op := mem_op and cond_met;
+	result_v.alu_jump := alu_jump and cond_met;
+	result_v.brpr := brpr and nop;
         
+	if (result_v.alu_jump = '0') and (brpr = '1') then
+		result_v.result := (others => '0');
+		result_v.result(prog_cnt'range) := std_logic_vector(unsigned(prog_cnt)+1);
+		--result_v.reg_op := '1';
+	end if;
+
 	alu_result <= result_v;
 	
 end process calc;