X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsrc%2Falu.vhd;h=c9e3aa20fa28b1f9cf2412737e66eddbdb7e9771;hb=1968f329b10681b760faec9369aa893cd2af8d44;hp=9883530306d497326980cf5405754c2d5a42289f;hpb=9b9e39f3672127dd87ea9dd022bddb3df3c2bef3;p=calu.git

diff --git a/cpu/src/alu.vhd b/cpu/src/alu.vhd
index 9883530..c9e3aa2 100755
--- a/cpu/src/alu.vhd
+++ b/cpu/src/alu.vhd
@@ -1,9 +1,31 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
 use work.alu_pkg.all;
+use work.extension_pkg.all;
 
 entity alu is
 	--some modules won't need all inputs
@@ -16,13 +38,25 @@ entity alu is
 			cond : in condition_t;
 			op_group : in op_info_t;
 			left_operand : in gp_register_t;
-			right_operand : in gp_register_t;
-                        displacement : in gp_register_t;
+			right_operand : in gp_register_t;
+			
+            displacement : in gp_register_t;
+			prog_cnt    : in instr_addr_t;
+			brpr	    : in std_logic;
+			
 			op_detail : in op_opt_t;
+			
 			alu_state  : in alu_result_rec;
-			alu_result : out alu_result_rec;
-                        addr : out gp_register_t;
-                        data : out gp_register_t
+			pval		: in gp_register_t;
+			pval_nxt    : in gp_register_t;
+			
+			alu_result : out alu_result_rec;
+            addr : out word_t; --memaddr
+            data : out gp_register_t; --mem data --ureg
+			
+			pinc : out std_logic;
+			pwr_en : out std_logic;
+			paddr : out paddr_t
 		);
 		
 end alu;