X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=cpu%2Fsim%2Ftestcore1.do;h=f2e2b79dabcb364f87f1a505f8b6ab04c00e8467;hb=61ccae8df4f138fd753bd1e5e7e8b8f25159d969;hp=f6b51b9ef364657a8ef4b4ab47df47c11d289a36;hpb=f79b90fff6c5992d835bcdac3252fa023adf4538;p=calu.git diff --git a/cpu/sim/testcore1.do b/cpu/sim/testcore1.do index f6b51b9..f2e2b79 100644 --- a/cpu/sim/testcore1.do +++ b/cpu/sim/testcore1.do @@ -5,6 +5,8 @@ vcom -work work ../src/mem_pkg.vhd vcom -work work ../src/rom.vhd vcom -work work ../src/rom_b.vhd vcom -work work ../src/r_w_ram.vhd +vcom -work work ../src/r_w_ram_be.vhd +vcom -work work ../src/r_w_ram_be_b.vhd vcom -work work ../src/r_w_ram_b.vhd vcom -work work ../src/r2_w_ram.vhd vcom -work work ../src/r2_w_ram_b.vhd @@ -39,7 +41,13 @@ vcom -work work ../src/extension.vhd vcom -work work ../src/extension_b.vhd +vcom -work work ../src/extension_imp_pkg.vhd +vcom -work work ../src/extension_imp.vhd +vcom -work work ../src/extension_imp_b.vhd +vcom -work work ../src/extension_7seg_pkg.vhd +vcom -work work ../src/extension_7seg.vhd +vcom -work work ../src/extension_7seg_b.vhd vcom -work work ../src/extension_uart_pkg.vhd vcom -work work ../src/rs232_tx.vhd @@ -68,6 +76,7 @@ add wave -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_r_add add wave -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_rd_data add wave -group fetchstageregister -radix hexadecimal /pipeline_tb/fetch_st/instruction add wave -group fetchstage -format logic /pipeline_tb/fetch_st/branch_prediction_bit +add wave -group fetchstage -format logic /pipeline_tb/fetch_st/rom_ram add wave -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/prediction_result add wave -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instruction @@ -124,25 +133,25 @@ add wave -group writebackstageregister -radix hexadecimal /pipeline_tb/writebac add wave -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_addr add wave -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/ram_data -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/ext_uart -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg_nxt -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/ext_reg +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/bus_rx +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/bus_tx +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co_nxt add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w2_uart_config add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w3_uart_send add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w4_uart_receive -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/data_out -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/new_tx_data -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/bus_tx -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/tx_data -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/tx_rdy -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/tx_rdy_int -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/sys_clk -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/cnt -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/stop_bit -add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/bd_rate - - -run 5000 ns +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/uart_data_read_nxt +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/ext_reg.sel +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_rx_inst/rx_data_nxt + +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/reg_we +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/write_en +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_en +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.dmem_write_en +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/ext_anysel +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/alu_jmp +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg.address +add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/data_ram_read +add wave -group test -radix hexadecimal /pipeline_tb/exec_st/dmem_write_en + +run 100000 ns