X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=3_test%2Fuartint.s;h=d2b7d58e2b7f20b97ea1b8ac4c57c6da17fdc9f6;hb=HEAD;hp=f1033f167a4f4c61758d1c9721f517059a8ab52e;hpb=505b47bec44e9d2cf079a0a70b7769bef88604cd;p=calu.git

diff --git a/3_test/uartint.s b/3_test/uartint.s
index f1033f1..d2b7d58 100644
--- a/3_test/uartint.s
+++ b/3_test/uartint.s
@@ -1,77 +1,112 @@
+.data
+str:
+	; "zlol"
+	.fill 0x5a4c4f4c
+	.fill 0x00000a0d
+
+int2hex:
+	;3210
+	.fill 0x33323130 
+	;7654
+	.fill 0x37363534
+	;ba98
+	.fill 0x62613938
+	;fedc
+	.fill 0x66656463
 .text
+	.define UART_BASE, 0x2000
+	.define UART_STATUS, 0x0
+	.define UART_RECV, 0xc
+	.define UART_TRANS, 0x8
+
+	.define UART_TRANS_EMPTY, 0x1
+	.define UART_RECV_NEW, 0x2
 start:
 	br+ main ;br+ 
-	call+ uartrdy ;call+ 0x80(128, 128)
+	br+ main
 	ret
 main:
-	ldi r1, 0x200b ;ldi r1, 8203
-	ldi r2, 0x200c ;ldi r2, 8204
-	ldi r3, 0x2010 ;ldi r3, 8208
-	ldi r4, 0x2024 ;ldi r4, 8228
-	ldi r5, 3
-	stw r5, 0(r4)
-	br+ start
-	; stwnv r5, 0(r4)
-uartrdy:
-	; load instructions into ram
-	ldi r8, 0x2034 ; paddr
-	ldi r9, 0x2038 ; pdata
 	xor r10, r10, r10
-	xor r11, r11, r11
+	xor r7, r7, r7
+	ldi r10, UART_BASE@lo
+	ldih r10, UART_BASE@hi
+	ldw r5, UART_STATUS(r10)
+	andx r5, UART_RECV_NEW
+	brzs+ main ; no new data?
+	ldw r7, UART_RECV(r10) ; load data
 
-	; place this small program into instr-ram:
-	;.text
-	;start:
-	;	br+ main
-	;	call+ main
-	;	ret
-	;main:
-	;	ldw r7, 0(r2)
-	;	stw r7, 0(r1)
-	;halt:
-	;	br+ halt
+	xor r1, r1, r1
+	xor r2, r2, r2
+	xor r3, r3, r3
+	ldi r1, str
+	ldi r2, 6
+	call send_string
+	xor r1, r1, r1
+	xor r2, r2, r2
+	ldi r1, 0x12bd
+	ldih r1, 0x1337
+	call debug_uint
+	ldi r1, 0x1337
+	ldih r1, 0x12bd
+	call debug_uint
 
-	;eb000183;br+ main;;
-	ldi r10, 0
-	stw r10, 0(r8)
-	ldi r11, 0x0183
-	ldih r11, 0xeb00
-	stw r11, 0(r9)
-	;eb000107;call+ main;;
-	xor r10, r10, r10
-	ldi r10, 1
-	stw r10, 0(r8)
-	ldi r11, 0x107
-	ldih r11, 0xeb00
-	stw r11, 0(r9)
-	;eb000008;ret;;
-	xor r10, r10, r10
-	ldi r10, 2
-	stw r10, 0(r8)
-	ldi r11, 0x8
-	ldih r11, 0xeb00
-	stw r11, 0(r9)
-	;e7390000;ldw r7, 0(r2);;
-	xor r10, r10, r10
-	ldi r10, 3
-	stw r10, 0(r8)
-	ldi r11, 0x0
-	ldih r11, 0xeb00
-	stw r11, 0(r9)
-	;e7b88000;stw r7, 0(r1);;
-	xor r10, r10, r10
-	ldi r10, 4
-	stw r10, 0(r8)
-	ldi r11, 0x8000
-	ldih r11, 0xe7b8
-	stw r11, 0(r9)
-	;eb000003;br+ halt;;
-	xor r10, r10, r10
-	ldi r10, 5
-	stw r10, 0(r8)
-	ldi r11, 0x3
-	ldih r11, 0xeb00
-	stw r11, 0(r9)
+main2:
+	ldw r5, UART_STATUS(r10)
+	andx r5, UART_RECV_NEW
+	brzs+ main2 ; no new data?
+	ldb r7, UART_RECV(r10) ; load data
+uartnrdy:
+	ldw r5, 0(r0)
+	andx r5, UART_TRANS_EMPTY
+	brnz+ uartnrdy ; transmitter not ready yet?
+	stw r7, UART_TRANS(r10) ; send zeh shit!
+	br main2 ; back to usual stuff
+
+send_string:
+	; r1 = addr
+	; r2 = len
+	addi r3, r1, 0
+send_string_int:
+	cmpi r2, 0
+	reteq-
+	ldb r1, 0(r3)
+	call send_byte
+	addis r2, r2, 0-1
+	addi r3, r3, 1
+	br send_string_int
+
+send_byte:
+	ldw r9, UART_STATUS(r10)
+	andx r9, UART_TRANS_EMPTY
+	brnz+ send_byte ; branch if not zero
+	stb r1, UART_TRANS(r10)
+	ret
 
-leave:
-	; just run and run, until we leave ROM and enter
+debug_uint:
+	addi r8, r1, 0
+	;usb_sendbuffersafe ("0x", 2);
+	xor r1, r1, r1
+	ldi r1, 0x30
+	call send_byte
+	xor r1, r1, r1
+	ldi r1, 0x78
+	call send_byte
+	;j = 0
+	xor r7, r7, r7
+	xor r6, r6, r6
+	ldi r6, int2hex@lo
+	ldih r6, int2hex@hi
+debug_unit_loop:
+	;for (j = 0; j < 8; ++j) {
+	cmpi r7, 8
+	reteq
+	;usb_sendbuffersafe (&int2hex[(i >> 28) & 0xf], 1);
+	lrs r1, r8, 28
+	andx r1, 0xf
+	add r9, r6, r1
+	ldb r1, 0(r9)
+	call send_byte
+	;i <<= 4;
+	lls r8, r8, 4
+	addi r7, r7, 1
+	br debug_unit_loop