X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;ds=sidebyside;f=src%2Fmainboard%2Fasus%2Fm5a99x-evo%2Fromstage.c;fp=src%2Fmainboard%2Fasus%2Fm5a99x-evo%2Fromstage.c;h=3f4ad35205fb78e2dbc92530acf4893610b46802;hb=7ea327f561bd48d59920caca527a65b6b60f7097;hp=8091f8e59fffbf3f7f1dd7d87ce64bddf765b023;hpb=5419d8b6bc32273faa65caf03e6771c7f4fc57fe;p=coreboot.git

diff --git a/src/mainboard/asus/m5a99x-evo/romstage.c b/src/mainboard/asus/m5a99x-evo/romstage.c
index 8091f8e59..3f4ad3520 100644
--- a/src/mainboard/asus/m5a99x-evo/romstage.c
+++ b/src/mainboard/asus/m5a99x-evo/romstage.c
@@ -46,7 +46,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/early_setup.c"
+#include "nb_cimx.h"
 #include <southbridge/amd/cimx/sb900/SbEarly.h>
 #include <southbridge/amd/cimx/sb900/SbPlatform.h> /* SB OEM constants */
 #include <southbridge/amd/cimx/sb900/smbus.h>
@@ -110,13 +110,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x32);
 
-	enable_rs780_dev8();
-	// sb800_clk_output_48Mhz();
-
 	it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 	printk(BIOS_DEBUG, "\n");
+	printk(BIOS_DEBUG, "zomg1\n");
+	sr56x0_rd890_disable_pcie_bridge();
+
+	printk(BIOS_DEBUG, "zomg2\n");
+	nb_Poweron_Init();
+	printk(BIOS_DEBUG, "zomg3\n");
+	nb_Ht_Init();
+	printk(BIOS_DEBUG, "zomg4\n");
+
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
@@ -170,7 +176,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x38);
 
 	/* run _early_setup before soft-reset. */
+#if 0
 	rs780_early_setup();
+#endif
 
 #if CONFIG_SET_FIDVID == 1
 	msr = rdmsr(0xc0010071);
@@ -190,7 +198,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 #endif
 
+#if 0
 	rs780_htinit();
+#endif
 
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
@@ -225,7 +235,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 //	die("After MCT init before CAR disabled.");
 
+#if 0
 	rs780_before_pci_init();
+#endif
 
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.