X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;ds=sidebyside;f=src%2Fbeh_pc_communication_tb.vhd;h=aa921e2dfc93bab00051a9a51a84fa4b83cb4f3a;hb=HEAD;hp=4efc777a9f1a4895ee5fa0d328b113ae9e9591bc;hpb=59c46d104154c881734b5dcdae684661dd56e6bd;p=hwmod.git

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index 4efc777..aa921e2 100644
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -14,22 +14,23 @@ end entity beh_pc_communication_tb;
 
 architecture sim of beh_pc_communication_tb is
 		type byte_file_type is file of hbyte;
+		subtype my_string is string(1 to 720);
 		signal sys_clk : std_logic;
 		signal sys_res_n : std_logic;
 		signal btn_a : std_logic;
 		signal tx_new : std_logic;
 		signal tx_done : std_logic;
 		signal rx_new : std_logic;
-		signal d_get : std_logic;
-		signal d_done : std_logic;
+		signal pc_get : std_logic;
+		signal pc_done : std_logic;
 		signal rx_data, tx_data : std_logic_vector(7 downto 0);
 
-		signal d_zeile : hzeile;
-		signal d_spalte : hspalte;
-		signal d_char : hbyte;
+		signal pc_zeile : hzeile;
+		signal pc_spalte : hspalte;
+		signal pc_char : hbyte;
 begin
-	-- display
-	inst : entity work.pc_communication(beh)
+	-- pc_communication
+	inst : pc_communication
 	port map (
 		sys_clk => sys_clk,
 		sys_res_n => sys_res_n,
@@ -47,11 +48,11 @@ begin
 		rx_new => rx_new,
 
 		-- History
-		d_zeile => d_zeile,
-		d_spalte => d_spalte,
-		d_get => d_get,
-		d_done => d_done,
-		d_char => d_char
+		pc_zeile => pc_zeile,
+		pc_spalte => pc_spalte,
+		pc_get => pc_get,
+		pc_done => pc_done,
+		pc_char => pc_char
 	);
 
 	clk : process
@@ -63,40 +64,68 @@ begin
 	end process clk;
 
 	stub_history : process
-		file f : byte_file_type open read_mode is "../../src/pc_communication.test";
-		variable rb : hbyte;
+		file f : text open read_mode is "../../src/pc_communication.test";
+		variable rb : character;
+		variable good : boolean;
+		variable i : integer;
+		variable buf : my_string;
+		variable l : line;
 	begin
-		wait until rising_edge(d_get);
+		pc_char <= (others => '0');
+		pc_done <= '0';
+		wait until sys_res_n = '1';
+
+		while not endfile (f) loop
+			readline(f, l);
+			buf := l.all;
+			i := 1;
+			while i < l'length loop
+				pc_done <= '0';
+				wait until rising_edge(pc_get);
+				wait for 150 ns;
+				pc_char <= (others => '0');
+				wait for 30 ns;
+				pc_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
+				i := i + 1;
+				pc_done <= '1';
+				wait for 30 ns;
+			end loop;
+		end loop;
+
 		assert not endfile(f) report "test beendet" severity failure;
-		read(f, rb);
-		wait for 30 ns;
-		d_char <= rb;
-		d_done <= '1';
-		wait for 15 ns;
-		d_done <= '0';
 	end process stub_history;
 
+	stub_uart : process
+	begin
+		tx_done <= '0';
+		wait until sys_res_n = '1';
+		while true loop
+			tx_done <= '0';
+			wait until rising_edge(tx_new);
+			wait for 300 ns;
+			tx_done <= '1';
+			wait for 30 ns;
+		end loop;
+	end process stub_uart;
+
 	reset_and_button : process
 	begin
 		-- init & reset
 		-- we only simulate pressing of button a by now!
 		sys_res_n <= '0';
-		btn_a <= '0';
-		d_done <= '0';
-		tx_data <= "00000000";
-		rx_data <= "00000000";
-		d_zeile <= "0000000";
-		d_spalte <= "0000000";
-		tx_new <= '0';
-		tx_done <= '0';
+		btn_a <= '1';
+		rx_data <= ( others => '0');
+		rx_new <= '0';
 		
 		wait for 90 ns;
 		sys_res_n <= '1';
 		wait for 30 ns;
-		btn_a <= '1';
-		wait for 15 ns;
 		btn_a <= '0';
+		wait for 30 ns;
+		btn_a <= '1';
 		wait;
+		--wait for 1000 ns;
+		--assert false report "test beendet" severity failure;
 	end process reset_and_button;
 
 end architecture sim;