X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;ds=sidebyside;f=cpu%2Fsrc%2Fwriteback_stage_b.vhd;h=307996ea3df2b8aa5c273f17aadc7bb6690ef8a5;hb=b333da851dda456b48f2a2535c4aeba143c657e1;hp=77fdf20a3b9144eba941f6476794cbb539745373;hpb=f8e429a38c3349e4b5578c367e5494a30b42e662;p=calu.git

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 77fdf20..307996e 100644
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -8,6 +8,7 @@ use work.core_pkg.all;
 use work.mem_pkg.all;
 use work.extension_pkg.all;
 use work.extension_uart_pkg.all;
+use work.extension_7seg_pkg.all;
 
 architecture behav of writeback_stage is
 
@@ -16,7 +17,7 @@ signal data_addr : word_t;
 
 signal wb_reg, wb_reg_nxt : writeback_rec;
 
-signal ext_uart,ext_timer,ext_gpmp :  extmod_rec;
+signal ext_uart,ext_timer,ext_gpmp,ext_7seg :  extmod_rec;
 
 signal sel_nxt, dmem_we, bus_rx :std_logic;
 
@@ -52,7 +53,20 @@ uart : extension_uart
 			bus_rx,
 			bus_tx
 		);
-
+	
+sseg : extension_7seg
+	generic map(
+		RESET_VALUE
+		)
+	port map(
+		clk,
+		reset,
+		ext_7seg,
+		sseg0,
+		sseg1,
+		sseg2,
+		sseg3
+		);
 	
 syn: process(clk, reset)
 
@@ -170,6 +184,12 @@ begin
   ext_uart.data <= (others => '0');
   ext_uart.addr <= (others => '0');
 
+  ext_7seg.sel <='0';
+  ext_7seg.wr_en <= wb_reg_nxt.dmem_write_en;
+  ext_7seg.byte_en <= (others => '0');
+  ext_7seg.data <= (others => '0');
+  ext_7seg.addr <= (others => '0');
+  
   ext_timer.sel <='0';
   ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
   ext_timer.byte_en <= (others => '0');
@@ -185,10 +205,10 @@ begin
  case wb_reg_nxt.address(31 downto 4) is
 	when EXT_UART_ADDR => 
 		ext_uart.sel <='1';
-		ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
+		ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
   		ext_uart.data <= ram_data;
 		ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
-		case wb_reg.address(1 downto 0) is
+		case wb_reg_nxt.address(1 downto 0) is
 				when "00" => ext_uart.byte_en <= "0001";
 				when "01" => ext_uart.byte_en <= "0010";
 				when "10" => ext_uart.byte_en <= "0100";
@@ -196,7 +216,21 @@ begin
 				when "11" => ext_uart.byte_en <= "1111";
 				when others => null;
 			end case;
-			
+
+	when EXT_7SEG_ADDR => 
+		ext_7seg.sel <='1';
+		ext_7seg.wr_en <= wb_reg_nxt.dmem_write_en;
+  		ext_7seg.data <= ram_data;
+		ext_7seg.addr <= wb_reg_nxt.address(31 downto 2);
+		ext_7seg.byte_en(1 downto 0) <= wb_reg_nxt.address(1 downto 0);
+
+--		case wb_reg_nxt.address(1 downto 0) is
+--			when "00" => ext_7seg.byte_en <= "0001";
+--			when "01" => ext_7seg.byte_en <= "0010";
+--			when "10" => ext_7seg.byte_en <= "0100";
+--			when "11" => ext_7seg.byte_en <= "1000";
+--			when others => null;
+--		end case;
 			
 	when EXT_TIMER_ADDR => 
  		ext_timer.sel <='1';