//
// This file may be distributed under the terms of the GNU LGPLv3 license.
-#include "vgatables.h" // struct VideoParamTableEntry_s
+#include "vgabios.h" // struct VideoParamTableEntry_s
#include "biosvar.h" // GET_GLOBAL
+#include "util.h" // memcpy_far
+#include "stdvga.h" // struct vgamode_s
/****************************************************************
* Video parameter table
****************************************************************/
+// Standard Video Save Pointer Table
+struct VideoSavePointer_s {
+ struct segoff_s videoparam;
+ struct segoff_s paramdynamicsave;
+ struct segoff_s textcharset;
+ struct segoff_s graphcharset;
+ struct segoff_s secsavepointer;
+ u8 reserved[8];
+} PACKED;
+
struct VideoSavePointer_s video_save_pointer_table VAR16;
-struct VideoParam_s video_param_table[] VAR16 = {
- // index=0x00 no mode defined
- {},
- // index=0x01 no mode defined
- {},
- // index=0x02 no mode defined
- {},
- // index=0x03 no mode defined
- {},
- // index=0x04 vga mode 0x04
- { 40, 24, 8, 0x0800, /* tw, th-1, ch, slength */
- { 0x09, 0x03, 0x00, 0x02 }, /* sequ_regs */
- 0x63, /* miscreg */
- { 0x2d, 0x27, 0x28, 0x90, 0x2b, 0x80, 0xbf, 0x1f,
- 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xa2,
- 0xff }, /* crtc_regs */
- { 0x00, 0x13, 0x15, 0x17, 0x02, 0x04, 0x06, 0x07,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x01, 0x00, 0x03, 0x00 }, /* actl_regs */
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0f, 0x0f, 0xff }, /* grdc_regs */
- },
- /* index=0x05 vga mode 0x05 */
- { 40, 24, 8, 0x0800, /* tw, th-1, ch, slength */
- { 0x09, 0x03, 0x00, 0x02 }, /* sequ_regs */
- 0x63, /* miscreg */
- { 0x2d, 0x27, 0x28, 0x90, 0x2b, 0x80, 0xbf, 0x1f,
- 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xa2,
- 0xff }, /* crtc_regs */
- { 0x00, 0x13, 0x15, 0x17, 0x02, 0x04, 0x06, 0x07,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x01, 0x00, 0x03, 0x00 }, /* actl_regs */
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0f, 0x0f, 0xff }, /* grdc_regs */
- },
- /* index=0x06 vga mode 0x06 */
- { 80, 24, 8, 0x1000, /* tw, th-1, ch, slength */
- { 0x01, 0x01, 0x00, 0x06 }, /* sequ_regs */
- 0x63, /* miscreg */
- { 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f,
- 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x9c, 0x8e, 0x8f, 0x28, 0x00, 0x96, 0xb9, 0xc2,
- 0xff }, /* crtc_regs */
- { 0x00, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
- 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
- 0x01, 0x00, 0x01, 0x00 }, /* actl_regs */
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x0f, 0xff }, /* grdc_regs */
- },
- /* index=0x07 vga mode 0x07 */
- { 80, 24, 16, 0x1000, /* tw, th-1, ch, slength */
- { 0x00, 0x03, 0x00, 0x02 }, /* sequ_regs */
- 0x66, /* miscreg */
- { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
- 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
- 0x9c, 0x8e, 0x8f, 0x28, 0x0f, 0x96, 0xb9, 0xa3,
- 0xff }, /* crtc_regs */
- { 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
- 0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x0e, 0x00, 0x0f, 0x08 }, /* actl_regs */
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0a, 0x0f, 0xff }, /* grdc_regs */
- },
- /* index=0x08 no mode defined */
- {},
- /* index=0x09 no mode defined */
- {},
- /* index=0x0a no mode defined */
- {},
- /* index=0x0b no mode defined */
- {},
- /* index=0x0c no mode defined */
- {},
- /* index=0x0d vga mode 0x0d */
- { 40, 24, 8, 0x2000, /* tw, th-1, ch, slength */
- { 0x09, 0x0f, 0x00, 0x06 }, /* sequ_regs */
- 0x63, /* miscreg */
- { 0x2d, 0x27, 0x28, 0x90, 0x2b, 0x80, 0xbf, 0x1f,
- 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xe3,
- 0xff }, /* crtc_regs */
- { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x01, 0x00, 0x0f, 0x00 }, /* actl_regs */
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff }, /* grdc_regs */
- },
- /* index=0x0e vga mode 0x0e */
- { 80, 24, 8, 0x4000, /* tw, th-1, ch, slength */
- { 0x01, 0x0f, 0x00, 0x06 }, /* sequ_regs */
- 0x63, /* miscreg */
- { 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f,
- 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x9c, 0x8e, 0x8f, 0x28, 0x00, 0x96, 0xb9, 0xe3,
- 0xff }, /* crtc_regs */
- { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x01, 0x00, 0x0f, 0x00 }, /* actl_regs */
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff }, /* grdc_regs */
- },
- /* index=0x0f no mode defined */
- {},
- /* index=0x10 no mode defined */
- {},
- /* index=0x11 vga mode 0x0f */
- { 80, 24, 14, 0x8000, /* tw, th-1, ch, slength */
- { 0x01, 0x0f, 0x00, 0x06 }, /* sequ_regs */
- 0xa3, /* miscreg */
- { 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f,
- 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x83, 0x85, 0x5d, 0x28, 0x0f, 0x63, 0xba, 0xe3,
- 0xff }, /* crtc_regs */
- { 0x00, 0x08, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00,
- 0x00, 0x08, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00,
- 0x01, 0x00, 0x01, 0x00 }, /* actl_regs */
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff }, /* grdc_regs */
- },
- /* index=0x12 vga mode 0x10 */
- { 80, 24, 14, 0x8000, /* tw, th-1, ch, slength */
- { 0x01, 0x0f, 0x00, 0x06 }, /* sequ_regs */
- 0xa3, /* miscreg */
- { 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f,
- 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x83, 0x85, 0x5d, 0x28, 0x0f, 0x63, 0xba, 0xe3,
- 0xff }, /* crtc_regs */
- { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
- 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
- 0x01, 0x00, 0x0f, 0x00 }, /* actl_regs */
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff }, /* grdc_regs */
- },
- /* index=0x13 no mode defined */
- {},
- /* index=0x14 no mode defined */
- {},
- /* index=0x15 no mode defined */
- {},
- /* index=0x16 no mode defined */
- {},
- /* index=0x17 vga mode 0x01 */
- { 40, 24, 16, 0x0800, /* tw, th-1, ch, slength */
- { 0x08, 0x03, 0x00, 0x02 }, /* sequ_regs */
- 0x67, /* miscreg */
- { 0x2d, 0x27, 0x28, 0x90, 0x2b, 0xa0, 0xbf, 0x1f,
- 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
- 0x9c, 0x8e, 0x8f, 0x14, 0x1f, 0x96, 0xb9, 0xa3,
- 0xff }, /* crtc_regs */
- { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
- 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
- 0x0c, 0x00, 0x0f, 0x08 }, /* actl_regs */
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x0f, 0xff }, /* grdc_regs */
- },
- /* index=0x18 vga mode 0x03 */
- { 80, 24, 16, 0x1000, /* tw, th-1, ch, slength */
- { 0x00, 0x03, 0x00, 0x02 }, /* sequ_regs */
- 0x67, /* miscreg */
- { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
- 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
- 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
- 0xff }, /* crtc_regs */
- { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
- 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
- 0x0c, 0x00, 0x0f, 0x08 }, /* actl_regs */
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x0f, 0xff }, /* grdc_regs */
- },
- /* index=0x19 vga mode 0x07 */
- { 80, 24, 16, 0x1000, /* tw, th-1, ch, slength */
- { 0x00, 0x03, 0x00, 0x02 }, /* sequ_regs */
- 0x66, /* miscreg */
- { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
- 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
- 0x9c, 0x8e, 0x8f, 0x28, 0x0f, 0x96, 0xb9, 0xa3,
- 0xff }, /* crtc_regs */
- { 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
- 0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x0e, 0x00, 0x0f, 0x08 }, /* actl_regs */
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0a, 0x0f, 0xff }, /* grdc_regs */
- },
- /* index=0x1a vga mode 0x11 */
- { 80, 29, 16, 0x0000, /* tw, th-1, ch, slength */
- { 0x01, 0x0f, 0x00, 0x06 }, /* sequ_regs */
- 0xe3, /* miscreg */
- { 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e,
- 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xea, 0x8c, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3,
- 0xff }, /* crtc_regs */
- { 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f,
- 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f,
- 0x01, 0x00, 0x0f, 0x00 }, /* actl_regs */
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff }, /* grdc_regs */
- },
- /* index=0x1b vga mode 0x12 */
- { 80, 29, 16, 0x0000, /* tw, th-1, ch, slength */
- { 0x01, 0x0f, 0x00, 0x06 }, /* sequ_regs */
- 0xe3, /* miscreg */
- { 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e,
- 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xea, 0x8c, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3,
- 0xff }, /* crtc_regs */
- { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
- 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
- 0x01, 0x00, 0x0f, 0x00 }, /* actl_regs */
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff }, /* grdc_regs */
- },
- /* index=0x1c vga mode 0x13 */
- { 40, 24, 8, 0x0000, /* tw, th-1, ch, slength */
- { 0x01, 0x0f, 0x00, 0x0e }, /* sequ_regs */
- 0x63, /* miscreg */
- { 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f,
- 0x00, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x9c, 0x8e, 0x8f, 0x28, 0x40, 0x96, 0xb9, 0xa3,
- 0xff }, /* crtc_regs */
- { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x41, 0x00, 0x0f, 0x00 }, /* actl_regs */
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, 0xff }, /* grdc_regs */
- },
- /* index=0x1d vga mode 0x6a */
- { 100, 36, 16, 0x0000, /* tw, th-1, ch, slength */
- { 0x01, 0x0f, 0x00, 0x06 }, /* sequ_regs */
- 0xe3, /* miscreg */
- { 0x7f, 0x63, 0x63, 0x83, 0x6b, 0x1b, 0x72, 0xf0,
- 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x59, 0x8d, 0x57, 0x32, 0x00, 0x57, 0x73, 0xe3,
- 0xff }, /* crtc_regs */
- { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
- 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
- 0x01, 0x00, 0x0f, 0x00 }, /* actl_regs */
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff }, /* grdc_regs */
- },
-};
+// standard BIOS Video Parameter Table
+struct VideoParam_s {
+ u8 twidth;
+ u8 theightm1;
+ u8 cheight;
+ u16 slength;
+ u8 sequ_regs[4];
+ u8 miscreg;
+ u8 crtc_regs[25];
+ u8 actl_regs[20];
+ u8 grdc_regs[9];
+} PACKED;
+
+struct VideoParam_s video_param_table[29] VAR16;
+
+void
+build_video_param(void)
+{
+ static u8 parammodes[ARRAY_SIZE(video_param_table)] VAR16 = {
+ 0, 0, 0, 0, 0x04, 0x05, 0x06, 0x07,
+ 0, 0, 0, 0, 0, 0x0d, 0x0e, 0,
+ 0, 0x0f, 0x10, 0, 0, 0, 0, 0x01,
+ 0x03, 0x07, 0x11, 0x12, 0x13
+ };
+
+ int i;
+ for (i=0; i<ARRAY_SIZE(parammodes); i++) {
+ u8 mode = GET_GLOBAL(parammodes[i]);
+ if (! mode)
+ continue;
+ struct VideoParam_s *vparam_g = &video_param_table[i];
+ struct vgamode_s *vmode_g = find_vga_entry(mode);
+ if (!vmode_g)
+ continue;
+ SET_VGA(vparam_g->twidth, GET_GLOBAL(vmode_g->twidth));
+ SET_VGA(vparam_g->theightm1, GET_GLOBAL(vmode_g->theight)-1);
+ SET_VGA(vparam_g->cheight, GET_GLOBAL(vmode_g->cheight));
+ SET_VGA(vparam_g->slength, GET_GLOBAL(vmode_g->slength));
+ memcpy_far(get_global_seg(), vparam_g->sequ_regs
+ , get_global_seg(), GET_GLOBAL(vmode_g->sequ_regs)
+ , ARRAY_SIZE(vparam_g->sequ_regs));
+ SET_VGA(vparam_g->miscreg, GET_GLOBAL(vmode_g->miscreg));
+ memcpy_far(get_global_seg(), vparam_g->crtc_regs
+ , get_global_seg(), GET_GLOBAL(vmode_g->crtc_regs)
+ , ARRAY_SIZE(vparam_g->crtc_regs));
+ memcpy_far(get_global_seg(), vparam_g->actl_regs
+ , get_global_seg(), GET_GLOBAL(vmode_g->actl_regs)
+ , ARRAY_SIZE(vparam_g->actl_regs));
+ memcpy_far(get_global_seg(), vparam_g->grdc_regs
+ , get_global_seg(), GET_GLOBAL(vmode_g->grdc_regs)
+ , ARRAY_SIZE(vparam_g->grdc_regs));
+ }
+
+ SET_VGA(video_save_pointer_table.videoparam
+ , SEGOFF(get_global_seg(), (u32)video_param_table));
+}
/****************************************************************
- * Palette definitions
+ * Register definitions
****************************************************************/
/* Mono */
0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00
};
+static u8 sequ_01[] VAR16 = { 0x08, 0x03, 0x00, 0x02 };
+static u8 crtc_01[] VAR16 = {
+ 0x2d, 0x27, 0x28, 0x90, 0x2b, 0xa0, 0xbf, 0x1f,
+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x14, 0x1f, 0x96, 0xb9, 0xa3,
+ 0xff };
+static u8 actl_01[] VAR16 = {
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
+ 0x0c, 0x00, 0x0f, 0x08 };
+static u8 grdc_01[] VAR16 = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x0f, 0xff };
+static u8 sequ_03[] VAR16 = { 0x00, 0x03, 0x00, 0x02 };
+static u8 crtc_03[] VAR16 = {
+ 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
+ 0xff };
+static u8 sequ_04[] VAR16 = { 0x09, 0x03, 0x00, 0x02 };
+static u8 crtc_04[] VAR16 = {
+ 0x2d, 0x27, 0x28, 0x90, 0x2b, 0x80, 0xbf, 0x1f,
+ 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xa2,
+ 0xff };
+static u8 actl_04[] VAR16 = {
+ 0x00, 0x13, 0x15, 0x17, 0x02, 0x04, 0x06, 0x07,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ 0x01, 0x00, 0x03, 0x00 };
+static u8 grdc_04[] VAR16 = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0f, 0x0f, 0xff };
+static u8 sequ_06[] VAR16 = { 0x01, 0x01, 0x00, 0x06 };
+static u8 crtc_06[] VAR16 = {
+ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f,
+ 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x28, 0x00, 0x96, 0xb9, 0xc2,
+ 0xff };
+static u8 actl_06[] VAR16 = {
+ 0x00, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
+ 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
+ 0x01, 0x00, 0x01, 0x00 };
+static u8 grdc_06[] VAR16 = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x0f, 0xff };
+static u8 crtc_07[] VAR16 = {
+ 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x28, 0x0f, 0x96, 0xb9, 0xa3,
+ 0xff };
+static u8 actl_07[] VAR16 = {
+ 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+ 0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+ 0x0e, 0x00, 0x0f, 0x08 };
+static u8 grdc_07[] VAR16 = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0a, 0x0f, 0xff };
+static u8 sequ_0d[] VAR16 = { 0x09, 0x0f, 0x00, 0x06 };
+static u8 crtc_0d[] VAR16 = {
+ 0x2d, 0x27, 0x28, 0x90, 0x2b, 0x80, 0xbf, 0x1f,
+ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xe3,
+ 0xff };
+static u8 actl_0d[] VAR16 = {
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ 0x01, 0x00, 0x0f, 0x00 };
+static u8 grdc_0d[] VAR16 = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff };
+static u8 sequ_0e[] VAR16 = { 0x01, 0x0f, 0x00, 0x06 };
+static u8 crtc_0e[] VAR16 = {
+ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f,
+ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x28, 0x00, 0x96, 0xb9, 0xe3,
+ 0xff };
+static u8 crtc_0f[] VAR16 = {
+ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f,
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x83, 0x85, 0x5d, 0x28, 0x0f, 0x63, 0xba, 0xe3,
+ 0xff };
+static u8 actl_0f[] VAR16 = {
+ 0x00, 0x08, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00,
+ 0x00, 0x08, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00,
+ 0x01, 0x00, 0x01, 0x00 };
+static u8 actl_10[] VAR16 = {
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
+ 0x01, 0x00, 0x0f, 0x00 };
+static u8 crtc_11[] VAR16 = {
+ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e,
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0xea, 0x8c, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3,
+ 0xff };
+static u8 actl_11[] VAR16 = {
+ 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f,
+ 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f,
+ 0x01, 0x00, 0x0f, 0x00 };
+static u8 sequ_13[] VAR16 = { 0x01, 0x0f, 0x00, 0x0e };
+static u8 crtc_13[] VAR16 = {
+ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f,
+ 0x00, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x28, 0x40, 0x96, 0xb9, 0xa3,
+ 0xff };
+static u8 actl_13[] VAR16 = {
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x41, 0x00, 0x0f, 0x00 };
+static u8 grdc_13[] VAR16 = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, 0xff };
+static u8 crtc_6A[] VAR16 = {
+ 0x7f, 0x63, 0x63, 0x83, 0x6b, 0x1b, 0x72, 0xf0,
+ 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x59, 0x8d, 0x57, 0x32, 0x00, 0x57, 0x73, 0xe3,
+ 0xff };
+
/****************************************************************
* Video mode list
#define VPARAM(x) &video_param_table[x]
static struct vgamode_s vga_modes[] VAR16 = {
- //mode vparam model bits sstart pelm dac
- {0x00, VPARAM(0x17), CTEXT, 4, SEG_CTEXT, 0xFF, PAL(palette2)},
- {0x01, VPARAM(0x17), CTEXT, 4, SEG_CTEXT, 0xFF, PAL(palette2)},
- {0x02, VPARAM(0x18), CTEXT, 4, SEG_CTEXT, 0xFF, PAL(palette2)},
- {0x03, VPARAM(0x18), CTEXT, 4, SEG_CTEXT, 0xFF, PAL(palette2)},
- {0x04, VPARAM(0x04), CGA, 2, SEG_CTEXT, 0xFF, PAL(palette1)},
- {0x05, VPARAM(0x05), CGA, 2, SEG_CTEXT, 0xFF, PAL(palette1)},
- {0x06, VPARAM(0x06), CGA, 1, SEG_CTEXT, 0xFF, PAL(palette1)},
- {0x07, VPARAM(0x07), MTEXT, 4, SEG_MTEXT, 0xFF, PAL(palette0)},
- {0x0D, VPARAM(0x0d), PLANAR4, 4, SEG_GRAPH, 0xFF, PAL(palette1)},
- {0x0E, VPARAM(0x0e), PLANAR4, 4, SEG_GRAPH, 0xFF, PAL(palette1)},
- {0x0F, VPARAM(0x11), PLANAR1, 1, SEG_GRAPH, 0xFF, PAL(palette0)},
- {0x10, VPARAM(0x12), PLANAR4, 4, SEG_GRAPH, 0xFF, PAL(palette2)},
- {0x11, VPARAM(0x1a), PLANAR1, 1, SEG_GRAPH, 0xFF, PAL(palette2)},
- {0x12, VPARAM(0x1b), PLANAR4, 4, SEG_GRAPH, 0xFF, PAL(palette2)},
- {0x13, VPARAM(0x1c), LINEAR8, 8, SEG_GRAPH, 0xFF, PAL(palette3)},
- {0x6A, VPARAM(0x1d), PLANAR4, 4, SEG_GRAPH, 0xFF, PAL(palette2)},
+ //mode model tx ty ch bits sstart slength
+ // pelm dac sequ misc crtc actl grdc
+ {0x00, CTEXT, 40, 25, 16, 4, SEG_CTEXT, 0x0800
+ , 0xFF, PAL(palette2), sequ_01, 0x67, crtc_01, actl_01, grdc_01 },
+ {0x01, CTEXT, 40, 25, 16, 4, SEG_CTEXT, 0x0800
+ , 0xFF, PAL(palette2), sequ_01, 0x67, crtc_01, actl_01, grdc_01 },
+ {0x02, CTEXT, 80, 25, 16, 4, SEG_CTEXT, 0x1000
+ , 0xFF, PAL(palette2), sequ_03, 0x67, crtc_03, actl_01, grdc_01 },
+ {0x03, CTEXT, 80, 25, 16, 4, SEG_CTEXT, 0x1000
+ , 0xFF, PAL(palette2), sequ_03, 0x67, crtc_03, actl_01, grdc_01 },
+ {0x04, CGA, 40, 25, 8, 2, SEG_CTEXT, 0x0800
+ , 0xFF, PAL(palette1), sequ_04, 0x63, crtc_04, actl_04, grdc_04},
+ {0x05, CGA, 40, 25, 8, 2, SEG_CTEXT, 0x0800
+ , 0xFF, PAL(palette1), sequ_04, 0x63, crtc_04, actl_04, grdc_04},
+ {0x06, CGA, 80, 25, 8, 1, SEG_CTEXT, 0x1000
+ , 0xFF, PAL(palette1), sequ_06, 0x63, crtc_06, actl_06, grdc_06},
+ {0x07, MTEXT, 80, 25, 16, 4, SEG_MTEXT, 0x1000
+ , 0xFF, PAL(palette0), sequ_03, 0x66, crtc_07, actl_07, grdc_07},
+ {0x0D, PLANAR4, 40, 25, 8, 4, SEG_GRAPH, 0x2000
+ , 0xFF, PAL(palette1), sequ_0d, 0x63, crtc_0d, actl_0d, grdc_0d},
+ {0x0E, PLANAR4, 80, 25, 8, 4, SEG_GRAPH, 0x4000
+ , 0xFF, PAL(palette1), sequ_0e, 0x63, crtc_0e, actl_0d, grdc_0d},
+ {0x0F, PLANAR1, 80, 25, 14, 1, SEG_GRAPH, 0x8000
+ , 0xFF, PAL(palette0), sequ_0e, 0xa3, crtc_0f, actl_0f, grdc_0d},
+ {0x10, PLANAR4, 80, 25, 14, 4, SEG_GRAPH, 0x8000
+ , 0xFF, PAL(palette2), sequ_0e, 0xa3, crtc_0f, actl_10, grdc_0d},
+ {0x11, PLANAR1, 80, 30, 16, 1, SEG_GRAPH, 0x0000
+ , 0xFF, PAL(palette2), sequ_0e, 0xe3, crtc_11, actl_11, grdc_0d},
+ {0x12, PLANAR4, 80, 30, 16, 4, SEG_GRAPH, 0x0000
+ , 0xFF, PAL(palette2), sequ_0e, 0xe3, crtc_11, actl_10, grdc_0d},
+ {0x13, LINEAR8, 40, 25, 8, 8, SEG_GRAPH, 0x0000
+ , 0xFF, PAL(palette3), sequ_13, 0x63, crtc_13, actl_13, grdc_13},
+ {0x6A, PLANAR4, 100, 37, 16, 4, SEG_GRAPH, 0x0000
+ , 0xFF, PAL(palette2), sequ_0e, 0xe3, crtc_6A, actl_10, grdc_0d},
};
struct vgamode_s *