Add dump support for the Winbond W83697SF.

[coreboot.git] / util / superiotool / winbond.c

diff --git a/util/superiotool/winbond.c b/util/superiotool/winbond.c
index faee986fba8c9aaa413d24ad475662490625fa04..44e0c4a3c658aafc3e9e1f9c5cbf9b1015f0ab50 100644 (file)
--- a/util/superiotool/winbond.c
+++ b/util/superiotool/winbond.c
@@ -299,7 +299,68 @@ const static struct superio_registers reg_table[] = {
                        {0x30,0x60,0x61,0x70,0xf0,EOT},
                        {0x00,0x00,0x00,0x00,0x00,EOT}},
                {EOT}}},
-       {0x68, "W83697SF/UF/UG", {      /* TODO: Add comment. */
+       {0x68, "W83697SF/UF/UG", {
+               /* ID:  0x68 (for W83697SF/UF/UG)
+                * Rev: 0x1X (for W83697SF)
+                *      0x0X (for W83697SF) -- sic!
+                *      0x1X (for W83697UF/UG)
+                */
+               {NOLDN, NULL,
+                       {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29,0x2a,
+                        0x2b,0x2c,EOT},
+                       {0x68,NANA,0xef,0xfe,MISC,0x00,0x00,0x00,0x00,MISC,
+                        0x00,0x30,EOT}},
+               {0x0, "Floppy",
+                       {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5,
+                        EOT},
+                       {0x01,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,0x00,0x00,
+                        EOT}},
+               {0x1, "Parallel port",
+                       {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
+                       {0x01,0x03,0x78,0x07,0x03,0x3f,EOT}},
+               {0x2, "COM1",
+                       {0x30,0x60,0x61,0x70,0xf0,EOT},
+                       {0x01,0x03,0xf8,0x04,0x00,EOT}},
+               {0x3, "COM2",
+                       {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
+                       {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}},
+               {0x7, "Game port, GPIO 1",
+                       {0x30,0x60,0x61,0x62,0x63,0xf0,0xf1,0xf2,EOT},
+                       {0x00,0x02,0x01,0x00,0x00,0xff,0x00,0x00,EOT}},
+               {0x8, "MIDI port, GPIO 5",
+                       {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3,
+                        0xf4,0xf5,EOT},
+                       {0x00,0x03,0x30,0x00,0x00,0x09,0xff,0x00,0x00,0x00,
+                        0x00,0x00,EOT}},
+               {0x9, "GPIO 2, GPIO 3, GPIO 4",
+                       {0x30,0x60,0x61,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,
+                        0xf7,0xf8,EOT},
+                       {0x00,0x00,0x00,0xff,0x00,0x00,0xff,0x00,0x00,0xff,
+                        0x00,0x00,EOT}},
+               {0xa, "ACPI",
+                       {0x30,0x70,0xf0,0xf1,0xf2,0xf3,0xf4,0xf6,0xf7,0xf9,
+                        0xfa,EOT},
+                       {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                        0x00,EOT}},
+               {0xb, "PWM",
+                       {0x30,0x60,0x61,EOT},
+                       {0x00,0x00,0x00,EOT}},
+               {0xc, "Smart card",
+                       {0x30,0x60,0x61,0x70,0xf0,EOT},
+                       {0x00,0x00,0x00,0x00,0x00,EOT}},
+               {0xd, "URC, GPIO 6",
+                       {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3,
+                        0xf4,EOT},
+                       {0x00,0x03,0xe8,0x00,0x00,0x00,0x00,0xff,0x00,0x00,
+                        0x00,EOT}},
+               {0xe, "URD, GPIO 7",
+                       {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3,
+                        EOT},
+                       {0x00,0x02,0xe8,0x00,0x00,0x00,0x00,0xff,0x00,0x00,
+                        EOT}},
+               {0xf, "GPIO 8",
+                       {0x30,0x60,0x61,0xf0,0xf1,0xf2,EOT},
+                       {0x00,0x00,0x00,0xff,0x00,0x00,EOT}},
                {EOT}}},
 
        /* ID[3..0] */