void probe_idregs_ali(uint16_t port);
void print_ali_chips(void);
+/* amd.c */
+void probe_idregs_amd(uint16_t port);
+void print_amd_chips(void);
+
/* serverengines.c */
void probe_idregs_serverengines(uint16_t port);
void print_serverengines_chips(void);
void probe_idregs_fintek_alternative(uint16_t port);
void print_fintek_chips(void);
+/* infineon.c */
+void probe_idregs_infineon(uint16_t port);
+void print_infineon_chips(void);
+
/* ite.c */
void probe_idregs_ite(uint16_t port);
void print_ite_chips(void);
{probe_idregs_nsc, {0x2e, 0x4e, 0x15c, 0x164e, EOT}},
/* I/O pairs on Nuvoton EC chips can be configured by firmware in
* addition to the following hardware strapping options. */
- {probe_idregs_nuvoton, {0x164e, 0x2e, EOT}},
+ {probe_idregs_nuvoton, {0x164e, 0x2e, 0x4e, EOT}},
{probe_idregs_smsc, {0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370, EOT}},
{probe_idregs_winbond, {0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}},
#ifdef PCI_SUPPORT
{probe_idregs_via, {0x3f0, EOT}},
+ /* in fact read the BASE from HW */
+ {probe_idregs_amd, {0xaa, EOT}},
#endif
{probe_idregs_serverengines, {0x2e, EOT}},
+ {probe_idregs_infineon, {0x2e, 0x4e}},
};
/** Table of functions to print out supported Super I/O chips. */
{print_winbond_chips},
#ifdef PCI_SUPPORT
{print_via_chips},
+ {print_amd_chips},
#endif
{print_serverengines_chips},
+ {print_infineon_chips},
};
#endif