regwrite(port, 0x02, 0x02); /* ITE */
}
+void enter_conf_mode_fintek_7777(uint16_t port)
+{
+ OUTB(0x77, port);
+ OUTB(0x77, port);
+}
+
+void exit_conf_mode_fintek_7777(uint16_t port)
+{
+ OUTB(0xaa, port); /* Fintek */
+}
+
int superio_unknown(const struct superio_registers reg_table[], uint16_t id)
{
return !strncmp(get_superio_name(reg_table, id), "<unknown>", 9);
}
+
const char *get_superio_name(const struct superio_registers reg_table[],
uint16_t id)
{
}
static void dump_regs(const struct superio_registers reg_table[],
- int i, int j, uint16_t port)
+ int i, int j, uint16_t port, uint8_t ldn_sel)
{
int k;
const int16_t *idx;
printf("LDN 0x%02x", reg_table[i].ldn[j].ldn);
if (reg_table[i].ldn[j].name != NULL)
printf(" (%s)", reg_table[i].ldn[j].name);
- regwrite(port, 0x07, reg_table[i].ldn[j].ldn);
+ regwrite(port, ldn_sel, reg_table[i].ldn[j].ldn);
} else {
- printf("Register dump:");
+ if (reg_table[i].ldn[j].name == NULL)
+ printf("Register dump:");
+ else
+ printf("(%s)", reg_table[i].ldn[j].name);
}
idx = reg_table[i].ldn[j].idx;
void dump_superio(const char *vendor,
const struct superio_registers reg_table[],
- uint16_t port, uint16_t id)
+ uint16_t port, uint16_t id, uint8_t ldn_sel)
{
int i, j, no_dump_available = 1;
if (reg_table[i].ldn[j].ldn == EOT)
break;
no_dump_available = 0;
- dump_regs(reg_table, i, j, port);
+ dump_regs(reg_table, i, j, port, ldn_sel);
}
if (no_dump_available)
}
}
+void dump_io(uint16_t iobase, uint16_t length)
+{
+ uint16_t i;
+
+ printf("Dumping %d I/O mapped registers at base 0x%04x:\n",
+ length, iobase);
+ for (i = 0; i < length; i++)
+ printf("%02x ", i);
+ printf("\n");
+ for (i = 0; i < length; i++)
+ printf("%02x ", INB(iobase + i));
+ printf("\n");
+}
+
void probing_for(const char *vendor, const char *info, uint16_t port)
{
if (!verbose)
print_version();
+#ifdef PCI_SUPPORT
+ /* Do some basic libpci init. */
+ pacc = pci_alloc();
+ pci_init(pacc);
+ pci_scan_bus(pacc);
+#endif
+
for (i = 0; i < ARRAY_SIZE(superio_ports_table); i++) {
for (j = 0; superio_ports_table[i].ports[j] != EOT; j++)
superio_ports_table[i].probe_idregs(