Enable -Werror for romcc

[coreboot.git] / util / romcc / tests / simple_test4.c

diff --git a/util/romcc/tests/simple_test4.c b/util/romcc/tests/simple_test4.c
index bfc05d9e0da6d8885bfaff140a055cd6529a86b2..2ac6a4d5f44d18d87d2859d9003dc575f1935e83 100644 (file)
--- a/util/romcc/tests/simple_test4.c
+++ b/util/romcc/tests/simple_test4.c
@@ -2,7 +2,7 @@
 #define HAVE_CAST_SUPPORT            1
 #define HAVE_STATIC_ARRAY_SUPPORT    1
 #define HAVE_POINTER_SUPPORT         1
-#define HAVE_CONSTANT_PROPOGATION    1
+#define HAVE_CONSTANT_PROPOGATION    0
 #define CALCULATE_DRB_REG            1
 
 void outb(unsigned char value, unsigned short port)
@@ -86,7 +86,7 @@ static void pcibios_write_config_dword(
 int log2(int value)
 {
        /* __builtin_bsr is a exactly equivalent to the x86 machine
-        * instruction with the exception that it returns -1  
+        * instruction with the exception that it returns -1
         * when the value presented to it is zero.
         * Otherwise __builtin_bsr returns the zero based index of
         * the highest bit set.
@@ -96,27 +96,27 @@ int log2(int value)
 
 
 /* Base Address */
-#ifndef TTYS0_BASE
-#define TTYS0_BASE 0x3f8
+#ifndef CONFIG_TTYS0_BASE
+#define CONFIG_TTYS0_BASE 0x3f8
 #endif
 
-#ifndef TTYS0_BAUD
-#define TTYS0_BAUD 115200
+#ifndef CONFIG_TTYS0_BAUD
+#define CONFIG_TTYS0_BAUD 115200
 #endif
 
-#if ((115200%TTYS0_BAUD) != 0)
+#if ((115200%CONFIG_TTYS0_BAUD) != 0)
 #error Bad ttys0 baud rate
 #endif
 
-#define TTYS0_DIV      (115200/TTYS0_BAUD)
+#define CONFIG_TTYS0_DIV       (115200/CONFIG_TTYS0_BAUD)
 
 /* Line Control Settings */
-#ifndef TTYS0_LCS
+#ifndef CONFIG_TTYS0_LCS
 /* Set 8bit, 1 stop bit, no parity */
-#define TTYS0_LCS      0x3
+#define CONFIG_TTYS0_LCS       0x3
 #endif
 
-#define UART_LCS       TTYS0_LCS
+#define UART_LCS       CONFIG_TTYS0_LCS
 
 /* Data */
 #define UART_RBR 0x00
@@ -138,7 +138,7 @@ int log2(int value)
 
 int uart_can_tx_byte(void)
 {
-       return inb(TTYS0_BASE + UART_LSR) & 0x20;
+       return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
 }
 
 void uart_wait_to_tx_byte(void)
@@ -149,14 +149,14 @@ void uart_wait_to_tx_byte(void)
 
 void uart_wait_until_sent(void)
 {
-       while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) 
+       while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
                ;
 }
 
 void uart_tx_byte(unsigned char data)
 {
        uart_wait_to_tx_byte();
-       outb(data, TTYS0_BASE + UART_TBR);
+       outb(data, CONFIG_TTYS0_BASE + UART_TBR);
        /* Make certain the data clears the fifos */
        uart_wait_until_sent();
 }
@@ -164,14 +164,14 @@ void uart_tx_byte(unsigned char data)
 void uart_init(void)
 {
        /* disable interrupts */
-       outb(0x0, TTYS0_BASE + UART_IER);
+       outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
        /* enable fifo's */
-       outb(0x01, TTYS0_BASE + UART_FCR);
+       outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
        /* Set Baud Rate Divisor to 12 ==> 115200 Baud */
-       outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
-       outb(TTYS0_DIV & 0xFF,   TTYS0_BASE + UART_DLL);
-       outb((TTYS0_DIV >> 8) & 0xFF,    TTYS0_BASE + UART_DLM);
-       outb(UART_LCS, TTYS0_BASE + UART_LCR);
+       outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
+       outb(CONFIG_TTYS0_DIV & 0xFF,   CONFIG_TTYS0_BASE + UART_DLL);
+       outb((CONFIG_TTYS0_DIV >> 8) & 0xFF,    CONFIG_TTYS0_BASE + UART_DLM);
+       outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
 }
 
 void __console_tx_char(unsigned char byte)
@@ -274,7 +274,7 @@ void print_spew(char *str) { __console_tx_string(str); }
 #define PM_BUS 0
 #define PM_DEVFN (PIIX4_DEVFN+3)
 
-#if HAVE_CONSTANT_PROPOGATION 
+#if HAVE_CONSTANT_PROPOGATION
 #define SMBUS_IO_BASE 0x1000
 #define SMBHSTSTAT 0
 #define SMBHSTCTL  2
@@ -428,7 +428,7 @@ static void spd_set_drb(void)
        unsigned end_of_memory;
        unsigned char device;
        unsigned char drb_reg;
-       
+
        end_of_memory = 0; /* in multiples of 8MiB */
        device = SMBUS_MEM_DEVICE_START;
 #if !CALCULATE_DRB_REG
@@ -464,13 +464,13 @@ static void spd_set_drb(void)
 #else
                        side1_bits += log2((((byte2 << 8) | byte));
 #endif
-                       
+
                        /* now I have the ram size in bits as a power of two (less 1) */
                        /* Make it mulitples of 8MB */
                        side1_bits -= 25;
 
                        /* side two */
-                       
+
                        /* number of physical banks */
                        byte = smbus_read_byte(device, 5);
                        if (byte > 1) {
@@ -487,7 +487,7 @@ static void spd_set_drb(void)
 #if CALCULATE_DRB_REG
                drb_reg = ((device - SMBUS_MEM_DEVICE_START) << 1) + 0x60;
 #endif
-               
+
 #if HAVE_STRING_SUPPORT
                print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n");
 #endif