Fix romstage creation with gcc 4.6 and CAR targets

[coreboot.git] / util / msrtool / k8.c

diff --git a/util/msrtool/k8.c b/util/msrtool/k8.c
index b85f66962fd93a8b88ef914165a5c60a754523a5..6d2500d40a13302a390ee47d0cbe06dd3e242b36 100644 (file)
--- a/util/msrtool/k8.c
+++ b/util/msrtool/k8.c
@@ -38,7 +38,7 @@ const struct msrdef k8_msrs[] = {
                }},
                { 13, 1, "LMSLE:", "Long Mode Segment Limit Enable", PRESENT_DEC, {
                        { MSR1(0), "Long mode segment limit check disabled" },
-                       { MSR1(1), "Long mode segment limit check enalbed" },
+                       { MSR1(1), "Long mode segment limit check enabled" },
                        { BITVAL_EOT }
                }},
                { 12, 1, "SVME:", "SVM Enable", PRESENT_DEC, {
@@ -134,7 +134,7 @@ const struct msrdef k8_msrs[] = {
                { BITS_EOT }
        }},
 
-       { 0xC0010015, MSRTYPE_RDWR, MSR2(0, 0), "HWCR Register", "This register controls the harware configuration", {
+       { 0xC0010015, MSRTYPE_RDWR, MSR2(0, 0), "HWCR Register", "This register controls the hardware configuration", {
                { 63, 32, RESERVED },
                { 31, 2, RESERVED },
                { 29, 6, "START_FID:", "Status of the startup FID", PRESENT_HEX, {
@@ -355,12 +355,5 @@ const struct msrdef k8_msrs[] = {
                { BITS_EOT }
        }},
 
-/*
-       { 0, MSRTYPE_RDONLY, MSR2(0, 0), "TEMPLATE", "Template MSR", {
-               { 63, 64, RESERVED },
-               { BITS_EOT }
-       }},
-*/
-
        { MSR_EOT }
 };