Enable -Werror for romcc

[coreboot.git] / util / inteltool / memory.c

diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index 256204c56348242638c3648a9a89c2e570a29928..18300ac4450a93efaf89642ed2833c15acb6cea4 100644 (file)
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -20,6 +20,7 @@
 
 #include <stdio.h>
 #include <stdlib.h>
+#include <inttypes.h>
 #include "inteltool.h"
 
 /*
@@ -109,6 +110,8 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
                printf("This northbridge does not have MCHBAR.\n");
                return 1;
        case PCI_DEVICE_ID_INTEL_GS45:
+       case PCI_DEVICE_ID_INTEL_X44:
+       case PCI_DEVICE_ID_INTEL_32X0:
                mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
                mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
                break;
@@ -128,9 +131,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
        }
 
        if (nb->device_id == PCI_DEVICE_ID_INTEL_82865)
-               printf("BAR6 = 0x%08llx (MEM)\n\n", mchbar_phys);
+               printf("BAR6 = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
        else
-               printf("MCHBAR = 0x%08llx (MEM)\n\n", mchbar_phys);
+               printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
 
        for (i = 0; i < size; i += 4) {
                if (*(uint32_t *)(mchbar + i))