Force coreboot mconf to create temp files in the output directory

[coreboot.git] / util / inteltool / inteltool.8

diff --git a/util/inteltool/inteltool.8 b/util/inteltool/inteltool.8
index daef6c2920a515e7b4d566361a780f0bbc6fd4aa..7b172f0ce83cc75d8bd184ffbcf60dd3f9f07047 100644 (file)
--- a/util/inteltool/inteltool.8
+++ b/util/inteltool/inteltool.8
@@ -1,15 +1,15 @@
-.TH INTELTOOL 8 "May 12, 2008"
+.TH INTELTOOL 8 "May 14, 2008"
 .SH NAME
 inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters
 .SH SYNOPSIS
-.B inteltool \fR[\fB\-vh?grpmedPM\fR]
+.B inteltool \fR[\fB\-vh?grpmedPMa\fR]
 .SH DESCRIPTION
 .B inteltool
 is a handy little tool for dumping the configuration space of Intel(R)
 CPUs, northbridges and southbridges.
-
+.sp
 This tool has been developed for the coreboot project (see
-.B http://www.coreboot.org/
+.B http://coreboot.org
 for details on coreboot).
 .SH OPTIONS
 .TP
@@ -20,31 +20,32 @@ Show a help text and exit.
 Show version information and exit.
 .TP
 .B "\-a, \-\-all"
-Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge and Intel(R) Core CPU MSRs.
+Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge
+and Intel(R) Core CPU MSRs.
 .TP
 .B "\-g, \-\-gpio"
-Dump I/O Controller Hub (ICH) southbridge GPIO registers
+Dump I/O Controller Hub (ICH) southbridge GPIO registers.
 .TP
 .B "\-r, \-\-rcba"
-Dump I/O Controller Hub (ICH) southbridge RCBA registers
+Dump I/O Controller Hub (ICH) southbridge RCBA registers.
 .TP
 .B "\-p, \-\-pmbase"
-Dump I/O Controller Hub (ICH) southbridge pmbase registers
+Dump I/O Controller Hub (ICH) southbridge PMBASE registers.
 .TP
 .B "\-m, \-\-mchbar"
-Dump Intel(R) northbridge MCHBAR registers
+Dump Intel(R) northbridge MCHBAR registers.
 .TP
 .B "\-e, \-\-epbar"
-Dump Intel(R) northbridge EPBAR registers
+Dump Intel(R) northbridge EPBAR registers.
 .TP
 .B "\-d, \-\-dmibar"
-Dump Intel(R) northbridge DMIBAR registers
+Dump Intel(R) northbridge DMIBAR registers.
 .TP
 .B "\-P, \-\-pciexbar"
-Dump Intel(R) northbridge PCIEXBAR registers
+Dump Intel(R) northbridge PCIEXBAR registers.
 .TP
 .B "\-M, \-\-msrs"
-Dump Intel(R) CPU MSRs
+Dump Intel(R) CPU MSRs.
 .SH BUGS
 Please report any bugs at
 .BR http://tracker.coreboot.org/trac/coreboot/newticket ","
@@ -52,15 +53,15 @@ or on the coreboot mailing list
 .RB "(" http://coreboot.org/Mailinglist ")."
 .SH LICENCE
 .B inteltool
-is covered by the GNU General Public License (GPL), version 2 or later.
+is covered by the GNU General Public License (GPL), version 2.
 .SH COPYRIGHT
-(C) 2008 coresystems GmbH
+Copyright (C) 2008 coresystems GmbH
 .SH AUTHORS
 Stefan Reinauer <stepan@coresystems.de>
 .PP
 This manual page was written by Stefan Reinauer <stepan@coresystems.de>.
 It is licensed under the terms of the GNU GPL (version 2).
-
-Intel(R) is a registered trademark of Intel Corporation. Other product and/or company names mentioned herein may be trademarks or registered trademarks of their respective owners.
-
-
+.sp
+Intel(R) is a registered trademark of Intel Corporation. Other product
+and/or company names mentioned herein may be trademarks or registered
+trademarks of their respective owners.