Merged revisions 7940-8026 via svnmerge from

[cacao.git] / src / vm / jit / sparc64 / md.c

diff --git a/src/vm/jit/sparc64/md.c b/src/vm/jit/sparc64/md.c
index 9a55c36954fe44cb8973025baba23e975b4091ae..af5c148fe7cccbb28c10037cae10c4d8b5942134 100644 (file)
--- a/src/vm/jit/sparc64/md.c
+++ b/src/vm/jit/sparc64/md.c
@@ -41,6 +41,11 @@
 #include "vm/jit/asmpart.h"
 #include "vm/jit/stacktrace.h"
 
+/* assembler function prototypes **********************************************/
+void asm_store_fp_state_reg(u8 *mem);
+void asm_load_fp_state_reg(u8 *mem);
+
+
 
 /* shift away 13-bit immediate,  mask rd and rs1    */
 #define SHIFT_AND_MASK(instr) \
@@ -146,48 +151,39 @@ u1 *md_codegen_get_pv_from_pc(u1 *ra)
 {
        u1 *pv;
        u8  mcode;
-       u4  mcode_masked;
-       s2  offset;
+       s4  offset;
 
        pv = ra;
 
        /* get the instruction word after jump and nop */
        mcode = *((u4 *) (ra+8) );
 
-       /* check if we have 2 instructions (ldah, lda) */
-
-       mcode_masked = SHIFT_AND_MASK(mcode);
-
-       if (mcode_masked == 0x40001) {
-#if 0
-               /* get displacement of first instruction (ldah) */
-
-               offset = (s4) (mcode << 16);
-               pv += offset;
-
-               /* get displacement of second instruction (lda) */
-
-               mcode = *((u4 *) (ra + 1 * 4));
-
-               assert((mcode >> 16) == 0x237b);
-
-               offset = (s2) (mcode & 0x0000ffff);
-               pv += offset;
+       /* check if we have a sethi insruction */
+       if (IS_SETHI(mcode)) {
+               s4 xor_imm;
+                               
+               /* get 22-bit immediate of sethi instruction */
+               offset = (s4) (mcode & 0x3fffff);
+               offset = offset << 10;
+               
+               /* now the xor */
+               mcode = *((u4 *) (ra+12) );
+               xor_imm = decode_13bit_imm(mcode);
+               
+               offset ^= xor_imm;       
+       }
+       else {
+               u4 mcode_masked;
+               
+               mcode_masked = SHIFT_AND_MASK(mcode);
 
-       } else {
-               /* get displacement of first instruction (lda) */
+               assert(mcode_masked == 0x40001);
 
-               assert((mcode >> 16) == 0x237a);
-#endif
                /* mask and extend the negative sign for the 13 bit immediate */
                offset = decode_13bit_imm(mcode);
-
-               pv += offset;
-       }
-       else
-       {
-               assert(0);
        }
+       
+       pv += offset;
 
        return pv;
 }
@@ -200,73 +196,84 @@ u1 *md_codegen_get_pv_from_pc(u1 *ra)
 
    INVOKESTATIC/SPECIAL:
 
-   dfdeffb8    ldx      [i5 - 72],o5
-   03c0f809    jmp      o5
-   00000000    nop
+   ????????    ldx      [i5 - 72],o5
+   ????????    jmp      o5             <-- ra
+   ????????    nop
+
+   w/ sethi (mptr in dseg out of 13-bit simm range)
+
+   ????????    sethi    hi(0x2000),o5
+   ????????    sub      i5,o5,o5
+   ????????    ldx      [o5 - 72],o5
+   ????????    jmp      o5             <-- ra
+   ????????    nop
 
    INVOKEVIRTUAL:
 
-   dc990000    ld       t9,0(a0)
-   df3e0000    ld       [g2 + 0],o5
-   03c0f809    jmp      o5
-   00000000    nop
+   ????????    ldx      [o0 + 0},g2
+   ????????    ldx      [g2 + 0],o5
+   ????????    jmp      o5             <-- ra
+   ????????    nop
 
    INVOKEINTERFACE:
 
-   dc990000    ld       t9,0(a0)
-   df39ff90    ld       [g2 - 112],g2
-   df3e0018    ld       [g2 + 24],o5
-   03c0f809    jmp      o5
-   00000000    nop
+   ????????    ldx      [o0 + 0},g2
+   ????????    ldx      [g2 - 112],g2
+   ????????    ldx      [g2 + 24],o5
+   ????????    jmp      o5             <-- ra
+   ????????    nop
 
 *******************************************************************************/
 
 u1 *md_get_method_patch_address(u1 *ra, stackframeinfo *sfi, u1 *mptr)
 {
-       u4  mcode, mcode_masked;
+       u4  mcode, mcode_sethi, mcode_masked;
        s4  offset;
        u1 *pa, *iptr;
 
        /* go back to the location of a possible sethi (3 instruction before jump) */
        /* note: ra is the address of the jump instruction on SPARC                */
-       iptr = ra - 3 * 4;
 
-       /* get first instruction word on current PC */
-
-       mcode = *((u4 *) iptr);
+       mcode_sethi = *((u4 *) (ra - 3 * 4));
 
        /* check for sethi instruction */
 
-       if (IS_SETHI(mcode)) {
-               /* XXX write a regression for this */
+       if (IS_SETHI(mcode_sethi)) {
+               u4 mcode_sub, mcode_ldx;
 
-               /* get 22-bit displacement of sethi instruction */
+               mcode_sub = *((u4 *) (ra - 2 * 4));
+               mcode_ldx = *((u4 *) (ra - 1 * 4));
 
-               offset = (s4) (mcode & 0x3fffff);
+               /* make sure the sequence of instructions is a loadhi */
+               if ((IS_SUB(mcode_sub)) && (IS_LDX_IMM(mcode_ldx)))
+               {
+
+
+               /* get 22-bit immediate of sethi instruction */
+
+               offset = (s4) (mcode_sethi & 0x3fffff);
                offset = offset << 10;
                
                /* goto next instruction */
-               iptr += 4;
-               mcode = *((u4 *) iptr);
                
                /* make sure it's a sub instruction (pv - big_disp) */
-               assert(IS_SUB(mcode));
+               assert(IS_SUB(mcode_sub));
                offset = -offset;
 
                /* get displacement of load instruction */
 
-               mcode = *((u4 *) (ra - 1 * 4));
-               assert(IS_LDX_IMM(mcode));
+               assert(IS_LDX_IMM(mcode_ldx));
 
-               offset += decode_13bit_imm(mcode);
+               offset += decode_13bit_imm(mcode_ldx);
                
                pa = sfi->pv + offset;
 
                return pa;
+               }
        }
 
-
-       /* simple (one-instruction) load */
+       /* we didn't find a sethi, or it didn't belong to a loadhi */
+       /* check for simple (one-instruction) load */
        iptr = ra - 1 * 4;
        mcode = *((u4 *) iptr);
 
@@ -327,6 +334,8 @@ void md_cacheflush(u1 *addr, s4 nbytes)
 void md_dcacheflush(u1 *addr, s4 nbytes)
 {
        /* XXX don't know yet */        
+       /* printf("md_dcacheflush\n"); */
+       __asm__ __volatile__ ( "membar 0x7F" : : : "memory" );
 }