* src/threads/atomic.cpp: New file.

[cacao.git] / src / vm / jit / sparc64 / md-atomic.hpp

diff --git a/src/vm/jit/sparc64/md-atomic.hpp b/src/vm/jit/sparc64/md-atomic.hpp
index ac4b616d107cec4cb5059f80a4301daf267e5e66..5539c38db0e0b04f22fa4199b4c3a4dc42617ee4 100644 (file)
--- a/src/vm/jit/sparc64/md-atomic.hpp
+++ b/src/vm/jit/sparc64/md-atomic.hpp
@@ -42,7 +42,7 @@
  *
  * @return value of the memory location before the store
  */
-inline static uint32_t Atomic_compare_and_swap_32(volatile uint32_t *p, uint32_t oldval, uint32_t newval)
+inline uint32_t Atomic::compare_and_swap(volatile uint32_t *p, uint32_t oldval, uint32_t newval)
 {
 #if 0
        // This one should be correct.
@@ -56,7 +56,7 @@ inline static uint32_t Atomic_compare_and_swap_32(volatile uint32_t *p, uint32_t
 
        return result;
 #else
-       return Atomic_generic_compare_and_swap_32(p, oldval, newval);
+       return generic_compare_and_swap(p, oldval, newval);
 #endif
 }
 
@@ -70,7 +70,7 @@ inline static uint32_t Atomic_compare_and_swap_32(volatile uint32_t *p, uint32_t
  *
  * @return value of the memory location before the store
  */
-inline static uint64_t Atomic_compare_and_swap_64(volatile uint64_t *p, uint64_t oldval, uint64_t newval)
+inline uint64_t Atomic::compare_and_swap(volatile uint64_t *p, uint64_t oldval, uint64_t newval)
 {
        uint64_t result;
 
@@ -93,23 +93,37 @@ inline static uint64_t Atomic_compare_and_swap_64(volatile uint64_t *p, uint64_t
  *
  * @return value of the memory location before the store
  */
-inline static void* Atomic_compare_and_swap_ptr(volatile void** p, void* oldval, void* newval)
+inline void* Atomic::compare_and_swap(volatile void** p, void* oldval, void* newval)
 {
-       return (void*) Atomic_compare_and_swap_64((volatile uint64_t*) p, (uint64_t) oldval, (uint64_t) newval);
+       return (void*) compare_and_swap((volatile uint64_t*) p, (uint64_t) oldval, (uint64_t) newval);
 }
 
 
 /**
  * A memory barrier.
  */
-inline static void Atomic_memory_barrier(void)
+inline void Atomic::memory_barrier(void)
 {
        __asm__ __volatile__ ("membar 0x0F" : : : "memory" );
 }
 
 
-#define STORE_ORDER_BARRIER() __asm__ __volatile__ ("wmb" : : : "memory");
-#define MEMORY_BARRIER_AFTER_ATOMIC() __asm__ __volatile__ ("mb" : : : "memory");
+/**
+ * A write memory barrier.
+ */
+inline void Atomic::write_memory_barrier(void)
+{
+       __asm__ __volatile__ ("wmb" : : : "memory");
+}
+
+
+/**
+ * An instruction barrier.
+ */
+inline void Atomic::instruction_barrier(void)
+{
+       __asm__ __volatile__ ("mb" : : : "memory");
+}
 
 #endif // _MD_ATOMIC_HPP