Changes:
- $Id: md-asm.h 5081 2006-07-06 13:59:01Z tbfg $
-
*/
#define itmp1 r11
#define itmp2 r12
-#define pv r13
+#define pv r14
-#define s0 r14
-#define s1 r15
+#define s0 r15
#define itmp3 r16
#define t0 r17
#define t5 r22
#define t6 r23
-#define s2 r24
-#define s3 r25
-#define s4 r26
-#define s5 r27
-#define s6 r28
-#define s7 r29
-#define s8 r30
-#define s9 r31
+#define s1 r24
+#define s2 r25
+#define s3 r26
+#define s4 r27
+#define s5 r28
+#define s6 r29
+#define s7 r30
+#define s8 r31
#define v0 a0
#define v1 a1
#define fa5 fr6
#define fa6 fr7
#define fa7 fr8
-
#define fa8 fr9
#define fa9 fr10
#define fa10 fr11
#define fa11 fr12
#define fa12 fr13
-#define fs0 fr14
-#define fs1 fr15
-
-#define ftmp1 fr16
-#define ftmp2 fr17
-
-#define ft0 fr18
-#define ft1 fr19
-#define ft2 fr20
-#define ft3 fr21
-#define ft4 fr22
-#define ft5 fr23
-
-#define fs2 fr24
-#define fs3 fr25
-#define fs4 fr26
-#define fs5 fr27
-#define fs6 fr28
-#define fs7 fr29
-#define fs8 fr30
-#define fs9 fr31
+#define ftmp1 fr14
+#define ftmp2 fr15
+
+#define fs0 fr16
+#define fs1 fr17
+#define fs2 fr18
+#define fs3 fr19
+#define fs4 fr20
+#define fs5 fr21
+#define fs6 fr22
+#define fs7 fr23
+#define fs8 fr24
+#define fs9 fr25
+#define fs10 fr26
+#define fs11 fr27
+#define fs12 fr28
+#define fs13 fr29
+#define fs14 fr30
+#define fs15 fr31
#define fv0 fa0
/* save and restore macros ****************************************************/
#define SAVE_ARGUMENT_REGISTERS(off) \
- stw a0,(0+(off))*4(sp); \
- stw a1,(1+(off))*4(sp); \
- stw a2,(2+(off))*4(sp); \
- stw a3,(3+(off))*4(sp); \
- stw a4,(4+(off))*4(sp); \
- stw a5,(5+(off))*4(sp); \
- stw a6,(6+(off))*4(sp); \
- stw a7,(7+(off))*4(sp); \
+ std a0,(0+(off))*8(sp); \
+ std a1,(1+(off))*8(sp); \
+ std a2,(2+(off))*8(sp); \
+ std a3,(3+(off))*8(sp); \
+ std a4,(4+(off))*8(sp); \
+ std a5,(5+(off))*8(sp); \
+ std a6,(6+(off))*8(sp); \
+ std a7,(7+(off))*8(sp); \
\
- stfd fa0,(8+(off))*4(sp); \
- stfd fa1,(10+(off))*4(sp); \
- stfd fa2,(12+(off))*4(sp); \
- stfd fa3,(14+(off))*4(sp); \
- stfd fa4,(16+(off))*4(sp); \
- stfd fa5,(18+(off))*4(sp); \
- stfd fa6,(20+(off))*4(sp); \
- stfd fa7,(22+(off))*4(sp);
+ stfd fa0,(8+(off))*8(sp); \
+ stfd fa1,(9+(off))*8(sp); \
+ stfd fa2,(10+(off))*8(sp); \
+ stfd fa3,(11+(off))*8(sp); \
+ stfd fa4,(12+(off))*8(sp); \
+ stfd fa5,(13+(off))*8(sp); \
+ stfd fa6,(14+(off))*8(sp); \
+ stfd fa7,(15+(off))*8(sp); \
+ stfd fa8,(16+(off))*8(sp); \
+ stfd fa9,(17+(off))*8(sp); \
+ stfd fa10,(18+(off))*8(sp);\
+ stfd fa11,(19+(off))*8(sp);\
+ stfd fa12,(20+(off))*8(sp);\
#define RESTORE_ARGUMENT_REGISTERS(off) \
- lwz a0,(0+(off))*4(sp); \
- lwz a1,(1+(off))*4(sp); \
- lwz a2,(2+(off))*4(sp); \
- lwz a3,(3+(off))*4(sp); \
- lwz a4,(4+(off))*4(sp); \
- lwz a5,(5+(off))*4(sp); \
- lwz a6,(6+(off))*4(sp); \
- lwz a7,(7+(off))*4(sp); \
+ ld a0,(0+(off))*8(sp); \
+ ld a1,(1+(off))*8(sp); \
+ ld a2,(2+(off))*8(sp); \
+ ld a3,(3+(off))*8(sp); \
+ ld a4,(4+(off))*8(sp); \
+ ld a5,(5+(off))*8(sp); \
+ ld a6,(6+(off))*8(sp); \
+ ld a7,(7+(off))*8(sp); \
\
- lfd fa0,(8+(off))*4(sp); \
- lfd fa1,(10+(off))*4(sp); \
- lfd fa2,(12+(off))*4(sp); \
- lfd fa3,(14+(off))*4(sp); \
- lfd fa4,(16+(off))*4(sp); \
- lfd fa5,(18+(off))*4(sp); \
- lfd fa6,(20+(off))*4(sp); \
- lfd fa7,(22+(off))*4(sp);
+ lfd fa0,(8+(off))*8(sp); \
+ lfd fa1,(9+(off))*8(sp); \
+ lfd fa2,(10+(off))*8(sp); \
+ lfd fa3,(11+(off))*8(sp); \
+ lfd fa4,(12+(off))*8(sp); \
+ lfd fa5,(13+(off))*8(sp); \
+ lfd fa6,(14+(off))*8(sp); \
+ lfd fa7,(15+(off))*8(sp); \
+ lfd fa8,(16+(off))*8(sp); \
+ lfd fa9,(17+(off))*8(sp); \
+ lfd fa10,(18+(off))*8(sp); \
+ lfd fa11,(19+(off))*8(sp); \
+ lfd fa12,(20+(off))*8(sp);
#define SAVE_TEMPORARY_REGISTERS(off) \
- stw t0,(0+(off))*4(sp); \
- stw t1,(1+(off))*4(sp); \
- stw t2,(2+(off))*4(sp); \
- stw t3,(3+(off))*4(sp); \
- stw t4,(4+(off))*4(sp); \
- stw t5,(5+(off))*4(sp); \
- stw t6,(6+(off))*4(sp); \
+ std t0,(0+(off))*8(sp); \
+ std t1,(1+(off))*8(sp); \
+ std t2,(2+(off))*8(sp); \
+ std t3,(3+(off))*8(sp); \
+ std t4,(4+(off))*8(sp); \
+ std t5,(5+(off))*8(sp); \
+ std t6,(6+(off))*8(sp);
+#if 0
\
- stfd ft0,(8+(off))*4(sp); \
- stfd ft1,(10+(off))*4(sp); \
- stfd ft2,(12+(off))*4(sp); \
- stfd ft3,(14+(off))*4(sp); \
- stfd ft4,(16+(off))*4(sp); \
- stfd ft5,(18+(off))*4(sp);
-
+ \
+ stfd ft0,(7+(off))*8(sp); \
+ stfd ft1,(8+(off))*8(sp); \
+ stfd ft2,(9+(off))*8(sp); \
+ stfd ft3,(10+(off))*8(sp); \
+ stfd ft4,(11+(off))*8(sp); \
+ stfd ft5,(12+(off))*8(sp);
+#endif
#define RESTORE_TEMPORARY_REGISTERS(off) \
- lwz t0,(0+(off))*4(sp); \
- lwz t1,(1+(off))*4(sp); \
- lwz t2,(2+(off))*4(sp); \
- lwz t3,(3+(off))*4(sp); \
- lwz t4,(4+(off))*4(sp); \
- lwz t5,(5+(off))*4(sp); \
- lwz t6,(6+(off))*4(sp); \
+ ld t0,(0+(off))*8(sp); \
+ ld t1,(1+(off))*8(sp); \
+ ld t2,(2+(off))*8(sp); \
+ ld t3,(3+(off))*8(sp); \
+ ld t4,(4+(off))*8(sp); \
+ ld t5,(5+(off))*8(sp); \
+ ld t6,(6+(off))*8(sp);
+#if 0
\
- lfd ft0,(8+(off))*4(sp); \
- lfd ft1,(10+(off))*4(sp); \
- lfd ft2,(12+(off))*4(sp); \
- lfd ft3,(14+(off))*4(sp); \
- lfd ft4,(16+(off))*4(sp); \
- lfd ft5,(18+(off))*4(sp);
-
+ \
+ lfd ft0,(7+(off))*8(sp); \
+ lfd ft1,(8+(off))*8(sp); \
+ lfd ft2,(9+(off))*8(sp); \
+ lfd ft3,(10+(off))*8(sp); \
+ lfd ft4,(11+(off))*8(sp); \
+ lfd ft5,(12+(off))*8(sp);
+#endif
#endif /* _MD_ASM_H */
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