* Formatted some macros a bit

[cacao.git] / src / vm / jit / powerpc / codegen.h

diff --git a/src/vm/jit/powerpc/codegen.h b/src/vm/jit/powerpc/codegen.h
index 1e118c3df0fdcff01e9c205bfc92533fcc53eb31..fb1c5de622fe5e2a3753aac2b9b99dc509792718 100644 (file)
--- a/src/vm/jit/powerpc/codegen.h
+++ b/src/vm/jit/powerpc/codegen.h
@@ -29,8 +29,9 @@
             Stefan Ring
 
    Changes: Christian Thalinger
+            Christian Ullrich
 
-   $Id: codegen.h 2693 2005-06-14 18:34:47Z twisti $
+   $Id: codegen.h 2920 2005-07-06 21:23:33Z twisti $
 
 */
 
@@ -46,6 +47,7 @@
 
 /* additional functions and macros to generate code ***************************/
 
+
 #if defined(STATISTICS)
 #define COUNT_SPILLS count_spills++
 #else
@@ -86,14 +88,14 @@
 #define M_INTMOVE(a,b) if ((a) != (b)) { M_MOV(a, b); }
 
 #define M_TINTMOVE(t,a,b) \
-       if ((t) == TYPE_LNG) { \
-               if ((a) <= (b)) \
-            M_INTMOVE(rd->secondregs[(a)], rd->secondregs[(b)]); \
-               M_INTMOVE((a), (b)); \
+    if ((t) == TYPE_LNG) { \
+        if ((a) <= (b)) \
+            M_INTMOVE(GET_LOW_REG((a)), GET_LOW_REG((b))); \
+        M_INTMOVE(GET_HIGH_REG((a)), GET_HIGH_REG((b))); \
         if ((a) > (b)) \
-            M_INTMOVE(rd->secondregs[(a)], rd->secondregs[(b)]); \
-       } else { \
-               M_INTMOVE((a), (b)); \
+            M_INTMOVE(GET_LOW_REG((a)), GET_LOW_REG((b))); \
+    } else { \
+        M_INTMOVE((a), (b)); \
     }
 
 
@@ -120,29 +122,64 @@
             number allready given to v)
 */
 
-#define var_to_reg_int0(regnr,v,tempnr,a,b) { \
-       if ((v)->flags & INMEMORY) { \
-               COUNT_SPILLS; \
-        if ((a)) M_ILD((tempnr), REG_SP, 4 * (v)->regoff); \
-               regnr = tempnr; \
-               if ((b) && IS_2_WORD_TYPE((v)->type)) \
-                       M_ILD((a) ? rd->secondregs[(tempnr)] : (tempnr), REG_SP, 4 * (v)->regoff + 4); \
-    } else \
-        regnr = (!(a) && (b)) ? rd->secondregs[(v)->regoff] : (v)->regoff; \
-}
-#define var_to_reg_int(regnr,v,tempnr) var_to_reg_int0(regnr,v,tempnr,1,1)
-
-
-#define var_to_reg_flt(regnr,v,tempnr) { \
-       if ((v)->flags & INMEMORY) { \
-               COUNT_SPILLS; \
-               if ((v)->type==TYPE_DBL) \
-                       M_DLD(tempnr,REG_SP,4*(v)->regoff); \
-               else \
-                       M_FLD(tempnr,REG_SP,4*(v)->regoff); \
-               regnr=tempnr; \
-       } else regnr=(v)->regoff; \
-}
+#define var_to_reg_int(regnr,v,tempnr) \
+       do { \
+               if ((v)->flags & INMEMORY) { \
+                       COUNT_SPILLS; \
+                       if (IS_2_WORD_TYPE((v)->type)) { \
+                               M_ILD(GET_HIGH_REG((tempnr)), REG_SP, (v)->regoff * 4); \
+                               M_ILD(GET_LOW_REG((tempnr)), REG_SP, (v)->regoff * 4 + 4); \
+                       } else \
+                               M_ILD((tempnr), REG_SP, (v)->regoff * 4); \
+                       regnr = tempnr; \
+               } else { \
+                       regnr = (v)->regoff; \
+               } \
+       } while(0)
+
+
+/* fetch only the low part of v, regnr hast to be a single register */
+
+#define var_to_reg_int_low(regnr,v,tempnr) \
+       do { \
+               if ((v)->flags & INMEMORY) { \
+                       COUNT_SPILLS; \
+                       M_ILD((tempnr), REG_SP, (v)->regoff * 4 + 4); \
+                       regnr = tempnr; \
+               } else { \
+                       regnr = GET_LOW_REG((v)->regoff); \
+               } \
+       } while(0)
+
+
+/* fetch only the high part of v, regnr hast to be a single register */
+
+#define var_to_reg_int_high(regnr,v,tempnr) \
+       do { \
+               if ((v)->flags & INMEMORY) { \
+                       COUNT_SPILLS; \
+                       M_ILD((tempnr), REG_SP, (v)->regoff * 4); \
+                       regnr = tempnr; \
+               } else { \
+                       regnr = GET_HIGH_REG((v)->regoff); \
+               } \
+       } while(0)
+
+
+
+#define var_to_reg_flt(regnr,v,tempnr) \
+       do { \
+               if ((v)->flags & INMEMORY) { \
+                       COUNT_SPILLS; \
+                       if ((v)->type == TYPE_DBL) \
+                               M_DLD(tempnr, REG_SP, (v)->regoff * 4); \
+                       else \
+                               M_FLD(tempnr, REG_SP, (v)->regoff * 4); \
+                       regnr = tempnr; \
+               } else { \
+                       regnr = (v)->regoff; \
+               } \
+       } while (0)
 
 
 /* store_reg_to_var_xxx:
@@ -155,13 +192,12 @@
     tempregnum ... Number of the temporary registers as returned by
                    reg_of_var.
 */     
-
 #define store_reg_to_var_int0(sptr, tempregnum, a, b) {       \
        if ((sptr)->flags & INMEMORY) {                    \
                COUNT_SPILLS;                                  \
-               if (a) M_IST(tempregnum, REG_SP, 4 * (sptr)->regoff); \
+               if (a) M_IST(GET_HIGH_REG((tempregnum)), REG_SP, 4 * (sptr)->regoff); \
                if ((b) && IS_2_WORD_TYPE((sptr)->type)) \
-                       M_IST(rd->secondregs[tempregnum], REG_SP, 4 * (sptr)->regoff + 4); \
+                       M_IST(GET_LOW_REG((tempregnum)), REG_SP, 4 * (sptr)->regoff + 4); \
                }                                              \
        }
 
@@ -188,8 +224,8 @@
     }
 
 #define LCONST(reg,c) \
-    ICONST((reg), (s4) ((s8) (c) >> 32)); \
-    ICONST(rd->secondregs[(reg)], (s4) ((s8) (c)));
+    ICONST(GET_HIGH_REG((reg)), (s4) ((s8) (c) >> 32));        \
+    ICONST(GET_LOW_REG((reg)), (s4) ((s8) (c)));
 
 
 #define M_COPY(from,to) \
@@ -331,7 +367,7 @@
 #define M_BLDU(a,b,c)                   M_OP2_IMM(34, a, b, c)
 #define M_SLDU(a,b,c)                   M_OP2_IMM(40, a, b, c)
 #define M_ILD(a,b,c)                    M_OP2_IMM(32, a, b, c)
-#define M_ALD(a,b,c)                    M_OP2_IMM(32, a, b, c)
+#define M_ALD(a,b,c)                    M_ILD(a, b, c)
 
 #define M_BSEXT(a,b)                    M_OP3(31, 954, 0, 0, a, b, 0)
 #define M_SSEXT(a,b)                    M_OP3(31, 922, 0, 0, a, b, 0)