-/* jit/powerpc/codegen.h - code generation macros and definitions for
- 32-bit powerpc
+/* vm/jit/powerpc/codegen.h - code generation macros and definitions for
+ 32-bit powerpc
- Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
- Institut f. Computersprachen, TU Wien
- R. Grafl, A. Krall, C. Kruegel, C. Oates, R. Obermaisser,
- M. Probst, S. Ring, E. Steiner, C. Thalinger, D. Thuernbeck,
- P. Tomsich, J. Wenninger
+ Copyright (C) 1996-2005 R. Grafl, A. Krall, C. Kruegel, C. Oates,
+ R. Obermaisser, M. Platter, M. Probst, S. Ring, E. Steiner,
+ C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, J. Wenninger,
+ Institut f. Computersprachen - TU Wien
This file is part of CACAO.
Authors: Andreas Krall
Stefan Ring
- $Id: codegen.h 598 2003-11-09 20:12:22Z twisti $
+ $Id: codegen.h 1735 2004-12-07 14:33:27Z twisti $
*/
#ifndef _CODEGEN_H
#define _CODEGEN_H
-#include "jit.h"
+#include "vm/global.h"
+#include "vm/jit/reg.h"
-/* see also file calling.doc for explanation of calling conventions */
+/* additional functions and macros to generate code ***************************/
-/* preallocated registers *****************************************************/
+#define BlockPtrOfPC(pc) ((basicblock *) iptr->target)
-/* integer registers */
-
-#define REG_RESULT 3 /* to deliver method results */
-//#define REG_RA 26 /* return address */
-#define REG_PV 13 /* procedure vector, must be provided by caller */
-#define REG_METHODPTR 12 /* pointer to the place from where the procedure */
- /* vector has been fetched */
-#define REG_ITMP1 11 /* temporary register */
-#define REG_ITMP2 12 /* temporary register and method pointer */
-#define REG_ITMP3 0 /* temporary register */
+#ifdef STATISTICS
+#define COUNT_SPILLS count_spills++
+#else
+#define COUNT_SPILLS
+#endif
-#define REG_ITMP1_XPTR 11 /* exception pointer = temporary register 1 */
-#define REG_ITMP2_XPC 12 /* exception pc = temporary register 2 */
-#define REG_SP 1 /* stack pointer */
-#define REG_ZERO 0 /* allways zero */
+/* gen_nullptr_check(objreg) */
-/* floating point registers */
+#define gen_nullptr_check(objreg) \
+ if (checknull) { \
+ M_TST((objreg)); \
+ M_BEQ(0); \
+ codegen_addxnullrefs(cd, mcodeptr); \
+ }
-#define REG_FRESULT 1 /* to deliver floating point method results */
-#define REG_FTMP1 16 /* temporary floating point register */
-#define REG_FTMP2 17 /* temporary floating point register */
-#define REG_FTMP3 0 /* temporary floating point register */
+#define gen_bound_check \
+ if (checkbounds) { \
+ M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));\
+ M_CMPU(s2, REG_ITMP3);\
+ M_BGE(0);\
+ codegen_addxboundrefs(cd, mcodeptr, s2); \
+ }
-#define REG_IFTMP 0 /* temporary integer and floating point register */
+/* MCODECHECK(icnt) */
-//#define INT_SAV_CNT 19 /* number of int callee saved registers */
-#define INT_ARG_CNT 8 /* number of int argument registers */
+#define MCODECHECK(icnt) \
+ if ((mcodeptr + (icnt)) > cd->mcodeend) \
+ mcodeptr = codegen_increase(cd, (u1 *) mcodeptr)
-//#define FLT_SAV_CNT 18 /* number of flt callee saved registers */
-#define FLT_ARG_CNT 13 /* number of flt argument registers */
+/* M_INTMOVE:
+ generates an integer-move from register a to b.
+ if a and b are the same int-register, no code will be generated.
+*/
+
+#define M_INTMOVE(a,b) if ((a) != (b)) { M_MOV(a, b); }
+
+#define M_TINTMOVE(t,a,b) \
+ if ((t) == TYPE_LNG) { \
+ if ((a) <= (b)) \
+ M_INTMOVE(rd->secondregs[(a)], rd->secondregs[(b)]); \
+ M_INTMOVE((a), (b)); \
+ if ((a) > (b)) \
+ M_INTMOVE(rd->secondregs[(a)], rd->secondregs[(b)]); \
+ } else { \
+ M_INTMOVE((a), (b)); \
+ }
+
+
+/* M_FLTMOVE:
+ generates a floating-point-move from register a to b.
+ if a and b are the same float-register, no code will be generated
+*/
+
+#define M_FLTMOVE(a,b) if ((a) != (b)) { M_FMOV(a, b); }
+
+
+/* var_to_reg_xxx:
+ this function generates code to fetch data from a pseudo-register
+ into a real register.
+ If the pseudo-register has actually been assigned to a real
+ register, no code will be emitted, since following operations
+ can use this register directly.
+
+ v: pseudoregister to be fetched from
+ tempregnum: temporary register to be used if v is actually spilled to ram
+
+ return: the register number, where the operand can be found after
+ fetching (this wil be either tempregnum or the register
+ number allready given to v)
+*/
+
+#define var_to_reg_int0(regnr,v,tempnr,a,b) { \
+ if ((v)->flags & INMEMORY) { \
+ COUNT_SPILLS; \
+ if ((a)) M_ILD((tempnr), REG_SP, 4 * (v)->regoff); \
+ regnr = tempnr; \
+ if ((b) && IS_2_WORD_TYPE((v)->type)) \
+ M_ILD((a) ? rd->secondregs[(tempnr)] : (tempnr), REG_SP, 4 * (v)->regoff + 4); \
+ } else \
+ regnr = (!(a) && (b)) ? rd->secondregs[(v)->regoff] : (v)->regoff; \
+}
+#define var_to_reg_int(regnr,v,tempnr) var_to_reg_int0(regnr,v,tempnr,1,1)
+
+
+#define var_to_reg_flt(regnr,v,tempnr) { \
+ if ((v)->flags & INMEMORY) { \
+ COUNT_SPILLS; \
+ if ((v)->type==TYPE_DBL) \
+ M_DLD(tempnr,REG_SP,4*(v)->regoff); \
+ else \
+ M_FLD(tempnr,REG_SP,4*(v)->regoff); \
+ regnr=tempnr; \
+ } else regnr=(v)->regoff; \
+}
+
+
+/* store_reg_to_var_xxx:
+ This function generates the code to store the result of an operation
+ back into a spilled pseudo-variable.
+ If the pseudo-variable has not been spilled in the first place, this
+ function will generate nothing.
+
+ v ............ Pseudovariable
+ tempregnum ... Number of the temporary registers as returned by
+ reg_of_var.
+*/
+
+#define store_reg_to_var_int0(sptr, tempregnum, a, b) { \
+ if ((sptr)->flags & INMEMORY) { \
+ COUNT_SPILLS; \
+ if (a) M_IST(tempregnum, REG_SP, 4 * (sptr)->regoff); \
+ if ((b) && IS_2_WORD_TYPE((sptr)->type)) \
+ M_IST(rd->secondregs[tempregnum], REG_SP, 4 * (sptr)->regoff + 4); \
+ } \
+ }
+
+#define store_reg_to_var_int(sptr, tempregnum) \
+ store_reg_to_var_int0(sptr, tempregnum, 1, 1)
+
+#define store_reg_to_var_flt(sptr, tempregnum) { \
+ if ((sptr)->flags & INMEMORY) { \
+ COUNT_SPILLS; \
+ if ((sptr)->type==TYPE_DBL) \
+ M_DST(tempregnum, REG_SP, 4 * (sptr)->regoff); \
+ else \
+ M_FST(tempregnum, REG_SP, 4 * (sptr)->regoff); \
+ } \
+ }
+
+
+#define ICONST(reg,c) \
+ if (((c) >= 0 && (c) <= 32767) || ((c) >= -32768 && (c) < 0)) {\
+ M_LDA((reg), REG_ZERO, (c)); \
+ } else { \
+ a = dseg_adds4(cd, c); \
+ M_ILD((reg), REG_PV, a); \
+ }
+
+#define LCONST(reg,c) \
+ ICONST((reg), (s4) ((s8) (c) >> 32)); \
+ ICONST(rd->secondregs[(reg)], (s4) ((s8) (c)));
+
+
+#define M_COPY(from,to) \
+ d = reg_of_var(rd, to, REG_IFTMP); \
+ if ((from->regoff != to->regoff) || \
+ ((from->flags ^ to->flags) & INMEMORY)) { \
+ if (IS_FLT_DBL_TYPE(from->type)) { \
+ var_to_reg_flt(s1, from, d); \
+ M_FLTMOVE(s1,d); \
+ store_reg_to_var_flt(to, d); \
+ }\
+ else { \
+ var_to_reg_int(s1, from, d); \
+ M_TINTMOVE(from->type,s1,d); \
+ store_reg_to_var_int(to, d); \
+ }\
+ }
+
+#define ALIGNCODENOP {if((int)((long)mcodeptr&7)){M_NOP;}}
/* macros to create code ******************************************************/
#define M_LDATST(a,b,c) M_ADDICTST(b, c, a)
#define M_CLR(a) M_IADD_IMM(0, 0, a)
+
/* function gen_resolvebranch **************************************************
parameters: ip ... pointer to instruction after branch (void*)
#define gen_resolvebranch(ip,so,to) \
*((s4*)(ip)-1)=(*((s4*)(ip)-1) & ~M_BRMASK) | (((s4)((to)-(so))+4)&((((*((s4*)(ip)-1)>>26)&63)==18)?M_BRAMASK:M_BRMASK))
-#define SOFTNULLPTRCHECK /* soft null pointer check supported as option */
-
/* function prototypes */
+
+void preregpass(methodinfo *m, registerdata *rd);
void docacheflush(u1 *p, long bytelen);
#endif /* _CODEGEN_H */
projects / cacao.git / blobdiff