Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
02110-1301, USA.
- Contact: cacao@cacaojvm.org
-
- Authors: Andreas Krall
- Reinhard Grafl
- Christian Thalinger
-
- $Id: md-os.c 7206 2007-01-11 22:39:52Z twisti $
+ $Id: md-os.c 8299 2007-08-13 08:41:18Z michi $
*/
#include <assert.h>
#include <sgidefs.h> /* required for _MIPS_SIM_ABI* defines (before signal.h) */
#include <signal.h>
+#include <stdint.h>
#include <ucontext.h>
#include "vm/types.h"
+#include "vm/jit/mips/codegen.h"
#include "vm/jit/mips/md-abi.h"
#include "mm/gc-common.h"
-#include "vm/exceptions.h"
+
#include "vm/signallocal.h"
-#include "vm/stringlocal.h"
+
#include "vm/jit/asmpart.h"
#include "vm/jit/stacktrace.h"
/* dummy allocation here to ensure that the GC is initialized. */
#if defined(ENABLE_GC_BOEHM)
- heap_allocate(1, 0, NULL);
+ (void) GCNEW(u1);
#endif
#if 0
void md_signal_handler_sigsegv(int sig, siginfo_t *siginfo, void *_p)
{
- ucontext_t *_uc;
- mcontext_t *_mc;
- greg_t *_gregs;
- u4 instr;
- ptrint addr;
- u1 *pv;
- u1 *sp;
- u1 *ra;
- u1 *xpc;
+ stackframeinfo sfi;
+ ucontext_t *_uc;
+ mcontext_t *_mc;
+ greg_t *_gregs;
+ u1 *pv;
+ u1 *sp;
+ u1 *ra;
+ u1 *xpc;
+ unsigned int cause;
+ u4 mcode;
+ int d;
+ int s1;
+ int16_t disp;
+ intptr_t val;
+ intptr_t addr;
+ int type;
+ void *p;
_uc = (struct ucontext *) _p;
_mc = &_uc->uc_mcontext;
sp = (u1 *) (ptrint) _gregs[REG_SP];
ra = (u1 *) (ptrint) _gregs[REG_RA]; /* this is correct for leafs */
-#if defined(__UCLIBC__)
- xpc = (u1 *) (ptrint) _gregs[CTX_EPC];
-#else
+#if !defined(__UCLIBC__) && ((__GLIBC__ == 2) && (__GLIBC_MINOR__ < 5))
+ /* NOTE: We only need this for pre glibc-2.5. */
+
xpc = (u1 *) (ptrint) _mc->pc;
+
+ /* get the cause of this exception */
+
+ cause = _mc->cause;
+
+ /* check the cause to find the faulting instruction */
+
+ /* TODO: use defines for that stuff */
+
+ switch (cause & 0x0000003c) {
+ case 0x00000008:
+ /* TLBL: XPC is ok */
+ break;
+
+ case 0x00000010:
+ /* AdEL: XPC is of the following instruction */
+ xpc = xpc - 4;
+ break;
+ }
+#else
+ xpc = (u1 *) (ptrint) _gregs[CTX_EPC];
#endif
- instr = *((u4 *) xpc);
- addr = _gregs[(instr >> 21) & 0x1f];
+ /* get exception-throwing instruction */
+
+ mcode = *((u4 *) xpc);
+
+ d = M_ITYPE_GET_RT(mcode);
+ s1 = M_ITYPE_GET_RS(mcode);
+ disp = M_ITYPE_GET_IMM(mcode);
+
+ /* check for special-load */
- if (addr == 0) {
- _gregs[REG_ITMP1_XPTR] =
- (ptrint) stacktrace_hardware_nullpointerexception(pv, sp, ra, xpc);
+ if (s1 == REG_ZERO) {
+ /* we use the exception type as load displacement */
- _gregs[REG_ITMP2_XPC] = (ptrint) xpc;
+ type = disp;
+ val = _gregs[d];
+ }
+ else {
+ /* This is a normal NPE: addr must be NULL and the NPE-type
+ define is 0. */
+
+ addr = _gregs[s1];
+ type = (s4) addr;
+ val = 0;
+ }
+
+ /* create stackframeinfo */
+
+ stacktrace_create_extern_stackframeinfo(&sfi, pv, sp, ra, xpc);
+
+ /* Handle the type. */
+
+ p = signal_handle(xpc, type, val);
+
+ /* remove stackframeinfo */
+
+ stacktrace_remove_stackframeinfo(&sfi);
+
+ /* set registers (only if exception object ready) */
+
+ if (p != NULL) {
+ _gregs[REG_ITMP1_XPTR] = (intptr_t) p;
+ _gregs[REG_ITMP2_XPC] = (intptr_t) xpc;
#if defined(__UCLIBC__)
- _gregs[CTX_EPC] = (ptrint) asm_handle_exception;
+ _gregs[CTX_EPC] = (intptr_t) asm_handle_exception;
#else
- _mc->pc = (ptrint) asm_handle_exception;
+ _mc->pc = (intptr_t) asm_handle_exception;
#endif
}
else {
- addr += (long) ((instr << 16) >> 16);
-
- throw_cacao_exception_exit(string_java_lang_InternalError,
- "faulting address: 0x%lx at 0x%lx\n",
- addr, xpc);
+#if defined(__UCLIBC__)
+ _gregs[CTX_EPC] = (intptr_t) xpc;
+#else
+ _mc->pc = (intptr_t) xpc;
+#endif
}
}
}
+/* md_critical_section_restart *************************************************
+
+ Search the critical sections tree for a matching section and set
+ the PC to the restart point, if necessary.
+
+*******************************************************************************/
+
#if defined(ENABLE_THREADS)
-void thread_restartcriticalsection(ucontext_t *_uc)
+void md_critical_section_restart(ucontext_t *_uc)
{
mcontext_t *_mc;
u1 *pc;