/* src/vm/jit/mips/emit.c - MIPS code emitter functions
- Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
- C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
- E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
- J. Wenninger, Institut f. Computersprachen - TU Wien
+ Copyright (C) 1996-2005, 2006, 2007, 2008
+ CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
This file is part of CACAO.
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
02110-1301, USA.
- $Id: emit.c 4398 2006-01-31 23:43:08Z twisti $
-
*/
#include "vm/jit/mips/codegen.h"
#include "vm/jit/mips/md-abi.h"
-#include "mm/memory.h"
+#include "mm/memory.hpp"
-#include "threads/lock-common.h"
+#include "threads/lock.hpp"
-#include "vm/builtin.h"
-#include "vm/exceptions.h"
-#include "vm/stringlocal.h" /* XXX for gen_resolvebranch */
+#include "vm/jit/builtin.hpp"
+#include "vm/options.h"
#include "vm/jit/abi.h"
#include "vm/jit/abi-asm.h"
#include "vm/jit/asmpart.h"
#include "vm/jit/dseg.h"
-#include "vm/jit/emit-common.h"
-#include "vm/jit/jit.h"
-#include "vm/jit/patcher-common.h"
-#include "vm/jit/replace.h"
-
-#include "vmcore/options.h"
+#include "vm/jit/emit-common.hpp"
+#include "vm/jit/jit.hpp"
+#include "vm/jit/patcher-common.hpp"
+#include "vm/jit/replace.hpp"
+#include "vm/jit/trace.hpp"
+#include "vm/jit/trap.hpp"
/* emit_load *******************************************************************
void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 opt)
{
- s4 checkdisp;
- s4 branchdisp;
-
- /* calculate the different displacements */
-
- checkdisp = (disp - 4);
- branchdisp = (disp - 4) >> 2;
+ // Calculate the displacements.
+ int32_t checkdisp = (disp - 4);
+ int32_t branchdisp = (disp - 4) >> 2;
/* check which branch to generate */
if (condition == BRANCH_UNCONDITIONAL) {
- /* check displacement for overflow */
-
- if ((checkdisp < (s4) 0xffff8000) || (checkdisp > (s4) 0x00007fff)) {
+ // Check displacement for overflow.
+ if (opt_AlwaysEmitLongBranches || ((checkdisp < (int32_t) 0xffff8000) || (checkdisp > (int32_t) 0x00007fff))) {
/* if the long-branches flag isn't set yet, do it */
if (!CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
CODEGENDATA_FLAG_LONGBRANCHES);
}
- vm_abort("emit_branch: emit unconditional long-branch code");
+ // Calculate the offset relative to PV.
+ int32_t currentrpc = cd->mcodeptr - cd->mcodebase;
+ int32_t offset = currentrpc + disp;
+
+ // Sanity check.
+ assert(offset % 4 == 0);
+
+ // Do the long-branch.
+ M_LUI(REG_ITMP3, offset >> 16);
+ M_OR_IMM(REG_ITMP3, offset, REG_ITMP3);
+ M_AADD(REG_PV, REG_ITMP3, REG_ITMP3);
+ M_JMP(REG_ITMP3);
+ M_NOP;
+ M_NOP; // This nop is to have 6 instructions (see BRANCH_NOPS).
}
else {
M_BR(branchdisp);
}
}
else {
- /* and displacement for overflow */
-
- if ((checkdisp < (s4) 0xffff8000) || (checkdisp > (s4) 0x00007fff)) {
+ // Check displacement for overflow.
+ if (opt_AlwaysEmitLongBranches || ((checkdisp < (int32_t) 0xffff8000) || (checkdisp > (int32_t) 0x00007fff))) {
/* if the long-branches flag isn't set yet, do it */
if (!CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
CODEGENDATA_FLAG_LONGBRANCHES);
}
+ // Calculate the offset relative to PV before we generate
+ // new code.
+ int32_t currentrpc = cd->mcodeptr - cd->mcodebase;
+ int32_t offset = currentrpc + disp;
+
+ // Sanity check.
+ assert(offset % 4 == 0);
+
switch (condition) {
case BRANCH_EQ:
M_BNE(GET_HIGH_REG(reg), GET_LOW_REG(reg), 5);
vm_abort("emit_branch: unknown condition %d", condition);
}
- /* The actual branch code which is over-jumped (NOTE: we
- don't use a branch delay slot here). */
+ // The actual branch code which is over-jumped. NOTE: We
+ // don't use a branch delay slot for the conditional
+ // branch.
- M_LUI(REG_ITMP3, branchdisp >> 16);
- M_OR_IMM(REG_ITMP3, branchdisp, REG_ITMP3);
+ // Do the long-branch.
+ M_LUI(REG_ITMP3, offset >> 16);
+ M_OR_IMM(REG_ITMP3, offset, REG_ITMP3);
M_AADD(REG_PV, REG_ITMP3, REG_ITMP3);
M_JMP(REG_ITMP3);
M_NOP;
-
}
else {
switch (condition) {
if (INSTRUCTION_MUST_CHECK(iptr)) {
M_BNEZ(reg, 2);
M_NOP;
- M_ALD_INTERN(REG_ZERO, REG_ZERO, EXCEPTION_HARDWARE_ARITHMETIC);
+ M_ALD_INTERN(REG_ZERO, REG_ZERO, TRAP_ArithmeticException);
}
}
void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
{
if (INSTRUCTION_MUST_CHECK(iptr)) {
- M_ILD_INTERN(REG_ITMP3, s1, OFFSET(java_arrayheader, size));
+ M_ILD_INTERN(REG_ITMP3, s1, OFFSET(java_array_t, size));
M_CMPULT(s2, REG_ITMP3, REG_ITMP3);
M_BNEZ(REG_ITMP3, 2);
M_NOP;
- M_ALD_INTERN(s2, REG_ZERO, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
+ M_ALD_INTERN(s2, REG_ZERO, TRAP_ArrayIndexOutOfBoundsException);
+ }
+}
+
+
+/* emit_arraystore_check *******************************************************
+
+ Emit an ArrayStoreException check.
+
+*******************************************************************************/
+
+void emit_arraystore_check(codegendata *cd, instruction *iptr)
+{
+ if (INSTRUCTION_MUST_CHECK(iptr)) {
+ M_BNEZ(REG_RESULT, 2);
+ M_NOP;
+ M_ALD_INTERN(REG_RESULT, REG_ZERO, TRAP_ArrayStoreException);
}
}
}
M_NOP;
- M_ALD_INTERN(s1, REG_ZERO, EXCEPTION_HARDWARE_CLASSCAST);
+ M_ALD_INTERN(s1, REG_ZERO, TRAP_ClassCastException);
}
}
if (INSTRUCTION_MUST_CHECK(iptr)) {
M_BNEZ(reg, 2);
M_NOP;
- M_ALD_INTERN(REG_ZERO, REG_ZERO, EXCEPTION_HARDWARE_NULLPOINTER);
+ M_ALD_INTERN(REG_ZERO, REG_ZERO, TRAP_NullPointerException);
}
}
if (INSTRUCTION_MUST_CHECK(iptr)) {
M_BNEZ(REG_RESULT, 2);
M_NOP;
- M_ALD_INTERN(REG_RESULT, REG_ZERO, EXCEPTION_HARDWARE_EXCEPTION);
+ M_ALD_INTERN(REG_RESULT, REG_ZERO, TRAP_CHECK_EXCEPTION);
}
}
+/* emit_trap_compiler **********************************************************
+
+ Emit a trap instruction which calls the JIT compiler.
+
+*******************************************************************************/
+
+void emit_trap_compiler(codegendata *cd)
+{
+ M_ALD_INTERN(REG_METHODPTR, REG_ZERO, TRAP_COMPILER);
+}
+
+
/* emit_trap *******************************************************************
Emit a trap instruction and return the original machine code.
uint32_t emit_trap(codegendata *cd)
{
- uint32_t mcode;
-
- /* Get machine code which is patched back in later. The
- trap is 1 instruction word long. */
+ // Get machine code which is patched back in later. The trap is 1
+ // instruction word long.
+ uint32_t mcode = *((uint32_t*) cd->mcodeptr);
- mcode = *((u4 *) cd->mcodeptr);
-
- M_ALD_INTERN(REG_ZERO, REG_ZERO, EXCEPTION_HARDWARE_PATCHER);
+ M_RESERVED;
return mcode;
}
void emit_verbosecall_enter(jitdata *jd)
{
methodinfo *m;
+ codeinfo *code;
codegendata *cd;
registerdata *rd;
methoddesc *md;
s4 disp;
- s4 i, j, t;
+ s4 i, s;
/* get required compiler data */
- m = jd->m;
- cd = jd->cd;
- rd = jd->rd;
+ m = jd->m;
+ code = jd->code;
+ cd = jd->cd;
+ rd = jd->rd;
md = m->parseddesc;
M_NOP;
- M_LDA(REG_SP, REG_SP, -(PA_SIZE + (2 + ARG_CNT + TMP_CNT) * 8));
- M_AST(REG_RA, REG_SP, PA_SIZE + 1 * 8);
+ /* keep stack 16-byte aligned */
+
+ M_LDA(REG_SP, REG_SP, -(PA_SIZE + (md->paramcount + 2 + TMP_CNT) * 8));
+ M_AST(REG_RA, REG_SP, PA_SIZE + md->paramcount * 8);
/* save argument registers (we store the registers as address
types, so it's correct for MIPS32 too) */
- for (i = 0; i < INT_ARG_CNT; i++)
- M_AST(abi_registers_integer_argument[i], REG_SP, PA_SIZE + (2 + i) * 8);
-
- for (i = 0; i < FLT_ARG_CNT; i++)
- M_DST(abi_registers_float_argument[i], REG_SP, PA_SIZE + (2 + INT_ARG_CNT + i) * 8);
+ for (i = 0; i < md->paramcount; i++) {
+ if (!md->params[i].inmemory) {
+ s = md->params[i].regoff;
+ switch (md->paramtypes[i].type) {
+ case TYPE_ADR:
+ case TYPE_INT:
+ M_AST(s, REG_SP, PA_SIZE + i * 8);
+ break;
+ case TYPE_LNG:
+ M_LST(s, REG_SP, PA_SIZE + i * 8);
+ break;
+ case TYPE_FLT:
+ M_FST(s, REG_SP, PA_SIZE + i * 8);
+ break;
+ case TYPE_DBL:
+ M_DST(s, REG_SP, PA_SIZE + i * 8);
+ break;
+ }
+ }
+ }
/* save temporary registers for leaf methods */
- if (jd->isleafmethod) {
+ if (code_is_leafmethod(code)) {
for (i = 0; i < INT_TMP_CNT; i++)
- M_AST(rd->tmpintregs[i], REG_SP, PA_SIZE + (2 + ARG_CNT + i) * 8);
+ M_AST(rd->tmpintregs[i], REG_SP, PA_SIZE + (md->paramcount + 2 + i) * 8);
for (i = 0; i < FLT_TMP_CNT; i++)
- M_DST(rd->tmpfltregs[i], REG_SP, PA_SIZE + (2 + ARG_CNT + INT_TMP_CNT + i) * 8);
+ M_DST(rd->tmpfltregs[i], REG_SP, PA_SIZE + (md->paramcount + 2 + INT_TMP_CNT + i) * 8);
}
- /* Load float arguments into integer registers. MIPS32 has less
- float argument registers than integer ones, we need to check
- that. */
-
- for (i = 0; i < md->paramcount && i < INT_ARG_CNT && i < FLT_ARG_CNT; i++) {
- t = md->paramtypes[i].type;
-
- if (IS_FLT_DBL_TYPE(t)) {
- if (IS_2_WORD_TYPE(t)) {
- M_DST(abi_registers_float_argument[i], REG_SP, 0 * 8);
- M_LLD(abi_registers_integer_argument[i], REG_SP, 0 * 8);
- }
- else {
- M_FST(abi_registers_float_argument[i], REG_SP, 0 * 8);
- M_ILD(abi_registers_integer_argument[i], REG_SP, 0 * 8);
- }
- }
- }
-
-#if SIZEOF_VOID_P == 4
- for (i = 0, j = 0; i < md->paramcount && i < TRACE_ARGS_NUM; i++) {
- t = md->paramtypes[i].type;
-
- if (IS_INT_LNG_TYPE(t)) {
- if (IS_2_WORD_TYPE(t)) {
- M_ILD(abi_registers_integer_argument[j], REG_SP, PA_SIZE + (2 + i) * 8);
- M_ILD(abi_registers_integer_argument[j + 1], REG_SP, PA_SIZE + (2 + i) * 8 + 4);
- }
- else {
-# if WORDS_BIGENDIAN == 1
- M_MOV(REG_ZERO, abi_registers_integer_argument[j]);
- M_ILD(abi_registers_integer_argument[j + 1], REG_SP, PA_SIZE + (2 + i) * 8);
-# else
- M_ILD(abi_registers_integer_argument[j], REG_SP, PA_SIZE + (2 + i) * 8);
- M_MOV(REG_ZERO, abi_registers_integer_argument[j + 1]);
-# endif
- }
- j += 2;
- }
- }
-#endif
-
disp = dseg_add_address(cd, m);
- M_ALD(REG_ITMP1, REG_PV, disp);
- M_AST(REG_ITMP1, REG_SP, PA_SIZE + 0 * 8);
- disp = dseg_add_functionptr(cd, builtin_verbosecall_enter);
+ M_ALD(REG_A0, REG_PV, disp);
+ M_LDA(REG_A1, REG_SP, PA_SIZE);
+ M_LDA(REG_A2, REG_SP, PA_SIZE + (md->paramcount + 2 + TMP_CNT) * 8 + cd->stackframesize * 8);
+ disp = dseg_add_functionptr(cd, trace_java_call_enter);
M_ALD(REG_ITMP3, REG_PV, disp);
M_JSR(REG_RA, REG_ITMP3);
M_NOP;
/* restore argument registers */
- for (i = 0; i < INT_ARG_CNT; i++)
- M_ALD(abi_registers_integer_argument[i], REG_SP, PA_SIZE + (2 + i) * 8);
-
- for (i = 0; i < FLT_ARG_CNT; i++)
- M_DLD(abi_registers_float_argument[i], REG_SP, PA_SIZE + (2 + INT_ARG_CNT + i) * 8);
+ for (i = 0; i < md->paramcount; i++) {
+ if (!md->params[i].inmemory) {
+ s = md->params[i].regoff;
+ switch (md->paramtypes[i].type) {
+ case TYPE_ADR:
+ case TYPE_INT:
+ M_ALD(s, REG_SP, PA_SIZE + i * 8);
+ break;
+ case TYPE_LNG:
+ M_LLD(s, REG_SP, PA_SIZE + i * 8);
+ break;
+ case TYPE_FLT:
+ M_FLD(s, REG_SP, PA_SIZE + i * 8);
+ break;
+ case TYPE_DBL:
+ M_DLD(s, REG_SP, PA_SIZE + i * 8);
+ break;
+ }
+ }
+ }
/* restore temporary registers for leaf methods */
- if (jd->isleafmethod) {
+ if (code_is_leafmethod(code)) {
for (i = 0; i < INT_TMP_CNT; i++)
- M_ALD(rd->tmpintregs[i], REG_SP, PA_SIZE + (2 + ARG_CNT + i) * 8);
+ M_ALD(rd->tmpintregs[i], REG_SP, PA_SIZE + (md->paramcount + 2 + i) * 8);
for (i = 0; i < FLT_TMP_CNT; i++)
- M_DLD(rd->tmpfltregs[i], REG_SP, PA_SIZE + (2 + ARG_CNT + INT_TMP_CNT + i) * 8);
+ M_DLD(rd->tmpfltregs[i], REG_SP, PA_SIZE + (md->paramcount + 2 + INT_TMP_CNT + i) * 8);
}
- M_ALD(REG_RA, REG_SP, PA_SIZE + 1 * 8);
- M_LDA(REG_SP, REG_SP, PA_SIZE + (2 + ARG_CNT + TMP_CNT) * 8);
+ /* keep stack 16-byte aligned */
+
+ M_ALD(REG_RA, REG_SP, PA_SIZE + md->paramcount * 8);
+ M_LDA(REG_SP, REG_SP, PA_SIZE + (md->paramcount + 2 + TMP_CNT) * 8);
/* mark trace code */
Generates the code for the call trace.
- void builtin_verbosecall_exit(s8 l, double d, float f, methodinfo *m);
-
*******************************************************************************/
#if !defined(NDEBUG)
M_NOP;
-#if SIZEOF_VOID_P == 8
- M_ASUB_IMM(REG_SP, 4 * 8, REG_SP); /* keep stack 16-byte aligned */
- M_AST(REG_RA, REG_SP, 0 * 8);
-
- M_LST(REG_RESULT, REG_SP, 1 * 8);
- M_DST(REG_FRESULT, REG_SP, 2 * 8);
+ /* keep stack 16-byte aligned */
- M_MOV(REG_RESULT, REG_A0);
- M_DMOV(REG_FRESULT, REG_FA1);
- M_FMOV(REG_FRESULT, REG_FA2);
-
- disp = dseg_add_address(cd, m);
- M_ALD(REG_A4, REG_PV, disp);
-#else
- M_ASUB_IMM(REG_SP, (8*4 + 4 * 8), REG_SP);
- M_AST(REG_RA, REG_SP, 8*4 + 0 * 8);
+#if SIZEOF_VOID_P == 8
+ assert(0); // XXX: Revisit this code for MIPS64!
+#endif
+ M_ASUB_IMM(REG_SP, PA_SIZE + 2 * 8, REG_SP);
+ M_AST(REG_RA, REG_SP, PA_SIZE + 1 * 8);
- M_LST(REG_RESULT_PACKED, REG_SP, 8*4 + 1 * 8);
- M_DST(REG_FRESULT, REG_SP, 8*4 + 2 * 8);
+ /* save return value */
switch (md->returntype.type) {
+ case TYPE_ADR:
+ case TYPE_INT:
+ M_AST(REG_RESULT, REG_SP, PA_SIZE + 0 * 8);
+ break;
case TYPE_LNG:
- M_LNGMOVE(REG_RESULT_PACKED, REG_A0_A1_PACKED);
+#if SIZEOF_VOID_P == 8
+ M_LST(REG_RESULT, REG_SP, PA_SIZE + 0 * 8);
+#else
+ M_LST(REG_RESULT_PACKED, REG_SP, PA_SIZE + 0 * 8);
+#endif
break;
-
- default:
-# if WORDS_BIGENDIAN == 1
- M_MOV(REG_ZERO, REG_A0);
- M_MOV(REG_RESULT, REG_A1);
-# else
- M_MOV(REG_RESULT, REG_A0);
- M_MOV(REG_ZERO, REG_A1);
-# endif
+ case TYPE_FLT:
+ M_FST(REG_FRESULT, REG_SP, PA_SIZE + 0 * 8);
+ break;
+ case TYPE_DBL:
+ M_DST(REG_FRESULT, REG_SP, PA_SIZE + 0 * 8);
}
- M_LLD(REG_A2_A3_PACKED, REG_SP, 8*4 + 2 * 8);
- M_FST(REG_FRESULT, REG_SP, 4*4 + 0 * 4);
-
disp = dseg_add_address(cd, m);
- M_ALD(REG_ITMP1, REG_PV, disp);
- M_AST(REG_ITMP1, REG_SP, 4*4 + 1 * 4);
-#endif
-
- disp = dseg_add_functionptr(cd, builtin_verbosecall_exit);
+ M_ALD(REG_A0, REG_PV, disp);
+ M_AADD_IMM(REG_SP, PA_SIZE, REG_A1);
+ disp = dseg_add_functionptr(cd, trace_java_call_exit);
M_ALD(REG_ITMP3, REG_PV, disp);
M_JSR(REG_RA, REG_ITMP3);
M_NOP;
-#if SIZEOF_VOID_P == 8
- M_DLD(REG_FRESULT, REG_SP, 2 * 8);
- M_LLD(REG_RESULT, REG_SP, 1 * 8);
+ /* restore return value */
- M_ALD(REG_RA, REG_SP, 0 * 8);
- M_AADD_IMM(REG_SP, 4 * 8, REG_SP);
+ switch (md->returntype.type) {
+ case TYPE_ADR:
+ case TYPE_INT:
+ M_ALD(REG_RESULT, REG_SP, PA_SIZE + 0 * 8);
+ break;
+ case TYPE_LNG:
+#if SIZEOF_VOID_P == 8
+ M_LLD(REG_RESULT, REG_SP, PA_SIZE + 0 * 8);
#else
- M_DLD(REG_FRESULT, REG_SP, 8*4 + 2 * 8);
- M_LLD(REG_RESULT_PACKED, REG_SP, 8*4 + 1 * 8);
-
- M_ALD(REG_RA, REG_SP, 8*4 + 0 * 8);
- M_AADD_IMM(REG_SP, 8*4 + 4 * 8, REG_SP);
+ M_LLD(REG_RESULT_PACKED, REG_SP, PA_SIZE + 0 * 8);
#endif
+ break;
+ case TYPE_FLT:
+ M_FLD(REG_FRESULT, REG_SP, PA_SIZE + 0 * 8);
+ break;
+ case TYPE_DBL:
+ M_DLD(REG_FRESULT, REG_SP, PA_SIZE + 0 * 8);
+ }
+
+ /* keep stack 16-byte aligned */
+
+ M_ALD(REG_RA, REG_SP, PA_SIZE + 1 * 8);
+ M_AADD_IMM(REG_SP, PA_SIZE + 2 * 8, REG_SP);
/* mark trace code */
projects / cacao.git / blobdiff