-/* vm/jit/mips/arch.h - architecture defines for MIPS
+/* src/vm/jit/mips/arch.h - architecture defines for MIPS
- Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
- R. Grafl, A. Krall, C. Kruegel, C. Oates, R. Obermaisser,
- M. Probst, S. Ring, E. Steiner, C. Thalinger, D. Thuernbeck,
- P. Tomsich, J. Wenninger
+ Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
+ C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
+ E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
+ J. Wenninger, Institut f. Computersprachen - TU Wien
This file is part of CACAO.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- 02111-1307, USA.
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA.
- Contact: cacao@complang.tuwien.ac.at
+ Contact: cacao@cacaojvm.org
Authors: Christian Thalinger
- $Id: arch.h 1638 2004-12-01 10:42:28Z twisti $
+ Changes:
+
+ $Id: arch.h 4357 2006-01-22 23:33:38Z twisti $
*/
#ifndef _ARCH_H
#define _ARCH_H
-/* preallocated registers *****************************************************/
-
-/* integer registers */
-
-#define REG_ZERO 0 /* always zero */
+#include "config.h"
-#define REG_RESULT 2 /* to deliver method results */
-#define REG_ITMP1 1 /* temporary register */
-#define REG_ITMP2 3 /* temporary register and method pointer */
-#define REG_ITMP3 25 /* temporary register */
-
-#define REG_ARG_0 4 /* argument register */
-#define REG_ARG_1 5 /* argument register */
-#define REG_ARG_2 6 /* argument register */
-#define REG_ARG_3 7 /* argument register */
-#define REG_ARG_4 8 /* argument register */
-#define REG_ARG_5 9 /* argument register */
+/* define architecture features ***********************************************/
-#define REG_RA 31 /* return address */
-#define REG_SP 29 /* stack pointer */
-#define REG_GP 28 /* global pointer */
+#define U8_AVAILABLE 1
-#define REG_PV 30 /* procedure vector, must be provided by caller */
-#define REG_METHODPTR 25 /* pointer to the place from where the procedure */
- /* vector has been fetched */
-#define REG_ITMP1_XPTR 1 /* exception pointer = temporary register 1 */
-#define REG_ITMP2_XPC 3 /* exception pc = temporary register 2 */
+#define USEBUILTINTABLE
+#if SIZEOF_VOID_P == 8
-/* floating point registers */
+#define SUPPORT_DIVISION 1
+#define SUPPORT_LONG 1
+#define SUPPORT_FLOAT 1
+#define SUPPORT_DOUBLE 1
-#define REG_FRESULT 0 /* to deliver floating point method results */
+#define SUPPORT_I2F 1
+#define SUPPORT_I2D 1
+#define SUPPORT_L2F 1
+#define SUPPORT_L2D 1
-#define REG_FTMP1 1 /* temporary floating point register */
-#define REG_FTMP2 2 /* temporary floating point register */
-#define REG_FTMP3 3 /* temporary floating point register */
+#define SUPPORT_F2I 0
+#define SUPPORT_F2L 0
+#define SUPPORT_D2I 0
+#define SUPPORT_D2L 0
-#define REG_IFTMP 1 /* temporary integer and floating point register */
+#define SUPPORT_LONG_ADD 1
+#define SUPPORT_LONG_CMP 1
+#define SUPPORT_LONG_CMP_CONST 1
+#define SUPPORT_LONG_LOGICAL 1
+#define SUPPORT_LONG_SHIFT 1
+#define SUPPORT_LONG_MUL 1
+#define SUPPORT_LONG_DIV 1
+#define SUPPORT_CONST_LOGICAL 1 /* AND, OR, XOR with immediates */
+#define SUPPORT_CONST_MUL 1 /* mutiply with immediate */
-#define INT_SAV_CNT 8 /* number of int callee saved registers */
-#define INT_ARG_CNT 8 /* number of int argument registers */
+#define SUPPORT_CONST_STORE 1 /* do we support const stores */
+#define SUPPORT_CONST_STORE_ZERO_ONLY 1 /* on some risc machines we can */
+ /* only store REG_ZERO */
-#define FLT_SAV_CNT 4 /* number of flt callee saved registers */
-#define FLT_ARG_CNT 8 /* number of flt argument registers */
+/* #define CONDITIONAL_LOADCONST 1 */
+#else /* SIZEOF_VOID_P == 8 */
-/* define architecture features ***********************************************/
+#define SUPPORT_DIVISION 1
+#define SUPPORT_LONG 1
+#define SUPPORT_FLOAT 1
+#define SUPPORT_DOUBLE 1
-#define POINTERSIZE 8
-#define WORDS_BIGENDIAN 1
+#define SUPPORT_I2F 0
+#define SUPPORT_I2D 0
+#define SUPPORT_L2F 0
+#define SUPPORT_L2D 0
-#define U8_AVAILABLE 1
+#define SUPPORT_F2I 0
+#define SUPPORT_F2L 0
+#define SUPPORT_D2I 0
+#define SUPPORT_D2L 0
-/* #define USE_CODEMMAP */
+#define SUPPORT_LONG_ADD 1
+#define SUPPORT_LONG_CMP 1
+#define SUPPORT_LONG_CMP_CONST 1
+#define SUPPORT_LONG_LOGICAL 1
+#define SUPPORT_LONG_SHIFT 0
+#define SUPPORT_LONG_MUL 0
+#define SUPPORT_LONG_DIV 0
-#define SUPPORT_DIVISION 0
-#define SUPPORT_LONG 1
-#define SUPPORT_FLOAT 1
-#define SUPPORT_DOUBLE 1
+#define SUPPORT_CONST_LOGICAL 1 /* AND, OR, XOR with immediates */
+#define SUPPORT_CONST_MUL 1 /* mutiply with immediate */
-#define SUPPORT_FMOD 1
-#define SUPPORT_IFCVT 1
-#define SUPPORT_FICVT 0
+#define SUPPORT_CONST_STORE 1 /* do we support const stores */
+#define SUPPORT_CONST_STORE_ZERO_ONLY 1 /* on some risc machines we can */
+ /* only store REG_ZERO */
-#define SUPPORT_LONG_ADD 1
-#define SUPPORT_LONG_CMP 1
-#define SUPPORT_LONG_LOG 1
-#define SUPPORT_LONG_SHIFT 1
-#define SUPPORT_LONG_MUL 1
-#define SUPPORT_LONG_DIV 0
-#define SUPPORT_LONG_ICVT 0
-#define SUPPORT_LONG_FCVT 1
+/* #define CONDITIONAL_LOADCONST 1 */
-#define SUPPORT_CONST_ASTORE 0 /* do we support const astores */
-#define SUPPORT_ONLY_ZERO_ASTORE 1 /* on risc machines we can only store */
- /* REG_ZERO */
-#define USEBUILTINTABLE
+#define SUPPORT_COMBINE_INTEGER_REGISTERS
+#define SUPPORT_PASS_FLOATARGS_IN_INTREGS
-/* #define CONDITIONAL_LOADCONST */
+#if defined(ENABLE_SOFT_FLOAT)
+# define SUPPORT_PASS_FLOATARGS_IN_INTREGS
+#endif
-/* #define CONSECUTIVE_INTARGS */
-/* #define CONSECUTIVE_FLOATARGS */
+#endif /* SIZEOF_VOID_P == 8 */
#endif /* _ARCH_H */
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