-/* vm/jit/i386/emit.c - i386 code emitter functions
+/* src/vm/jit/i386/emit.c - i386 code emitter functions
Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
Authors: Christian Thalinger
- $Id: emit.c 5109 2006-07-11 19:17:23Z twisti $
+ Changes:
+
+ $Id: emit.c 5401 2006-09-07 12:52:31Z twisti $
*/
#include "vm/types.h"
-#include "vm/statistics.h"
-#include "vm/jit/emit.h"
-#include "vm/jit/jit.h"
#include "vm/jit/i386/md-abi.h"
#include "vm/jit/i386/md-emit.h"
#include "vm/jit/i386/codegen.h"
+#if defined(ENABLE_THREADS)
+# include "threads/native/lock.h"
+#endif
-/* emit_load_s1 ****************************************************************
+#include "vm/builtin.h"
+#include "vm/statistics.h"
+#include "vm/jit/asmpart.h"
+#include "vm/jit/dseg.h"
+#include "vm/jit/emit.h"
+#include "vm/jit/jit.h"
+#include "vm/jit/replace.h"
- Emits a possible load of the first source operand.
+
+/* emit_load ******************************************************************
+
+ Emits a possible load of an operand.
*******************************************************************************/
-s4 emit_load_s1(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
+inline s4 emit_load(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
{
codegendata *cd;
s4 disp;
cd = jd->cd;
- if (src->flags & INMEMORY) {
+ if (IS_INMEMORY(src->flags)) {
COUNT_SPILLS;
disp = src->regoff * 4;
M_DLD(tempreg, REG_SP, disp);
else
M_FLD(tempreg, REG_SP, disp);
-
- } else {
+ }
+ else {
if (IS_2_WORD_TYPE(src->type))
M_LLD(tempreg, REG_SP, disp);
else
}
reg = tempreg;
- } else
+ }
+ else
reg = src->regoff;
return reg;
}
-/* emit_load_s2 ****************************************************************
+/* emit_load_low ************************************************************
- Emits a possible load of the second source operand.
+ Emits a possible load of the low 32-bits of an operand.
*******************************************************************************/
-s4 emit_load_s2(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
+inline s4 emit_load_low(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
{
codegendata *cd;
s4 disp;
s4 reg;
+ assert(src->type == TYPE_LNG);
+
/* get required compiler data */
cd = jd->cd;
- if (src->flags & INMEMORY) {
+
+ if (IS_INMEMORY(src->flags)) {
COUNT_SPILLS;
disp = src->regoff * 4;
- if (IS_FLT_DBL_TYPE(src->type)) {
- if (IS_2_WORD_TYPE(src->type))
- M_DLD(tempreg, REG_SP, disp);
- else
- M_FLD(tempreg, REG_SP, disp);
-
- } else {
- if (IS_2_WORD_TYPE(src->type))
- M_LLD(tempreg, REG_SP, disp);
- else
- M_ILD(tempreg, REG_SP, disp);
- }
+ M_ILD(tempreg, REG_SP, disp);
reg = tempreg;
- } else
- reg = src->regoff;
+ }
+ else
+ reg = GET_LOW_REG(src->regoff);
return reg;
}
-/* emit_load_s3 ****************************************************************
+/* emit_load_high ***********************************************************
- Emits a possible load of the third source operand.
+ Emits a possible load of the high 32-bits of an operand.
*******************************************************************************/
-s4 emit_load_s3(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
+inline s4 emit_load_high(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
{
codegendata *cd;
s4 disp;
/* get required compiler data */
+ assert(src->type == TYPE_LNG);
+
cd = jd->cd;
- if (src->flags & INMEMORY) {
+ if (IS_INMEMORY(src->flags)) {
COUNT_SPILLS;
disp = src->regoff * 4;
- if (IS_FLT_DBL_TYPE(src->type)) {
- if (IS_2_WORD_TYPE(src->type))
- M_DLD(tempreg, REG_SP, disp);
- else
- M_FLD(tempreg, REG_SP, disp);
-
- } else {
- if (IS_2_WORD_TYPE(src->type))
- M_LLD(tempreg, REG_SP, disp);
- else
- M_ILD(tempreg, REG_SP, disp);
- }
+ M_ILD(tempreg, REG_SP, disp + 4);
reg = tempreg;
- } else
- reg = src->regoff;
+ }
+ else
+ reg = GET_HIGH_REG(src->regoff);
return reg;
}
-/* emit_load_s1_low ************************************************************
+/* emit_load_s1 ****************************************************************
- Emits a possible load of the low 32-bits of the first long source
- operand.
+ Emits a possible load of the first source operand.
*******************************************************************************/
-s4 emit_load_s1_low(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
+s4 emit_load_s1(jitdata *jd, instruction *iptr, s4 tempreg)
{
- codegendata *cd;
- s4 disp;
+ stackptr src;
s4 reg;
- assert(src->type == TYPE_LNG);
+ /* get required compiler data */
+
+ src = iptr->s1.var;
+
+ reg = emit_load(jd, iptr, src, tempreg);
+
+ return reg;
+}
+
+
+/* emit_load_s2 ****************************************************************
+
+ Emits a possible load of the second source operand.
+
+*******************************************************************************/
+
+s4 emit_load_s2(jitdata *jd, instruction *iptr, s4 tempreg)
+{
+ stackptr src;
+ s4 reg;
/* get required compiler data */
- cd = jd->cd;
+ src = iptr->sx.s23.s2.var;
- if (src->flags & INMEMORY) {
- COUNT_SPILLS;
+ reg = emit_load(jd, iptr, src, tempreg);
+
+ return reg;
+}
- disp = src->regoff * 4;
- M_ILD(tempreg, REG_SP, disp);
+/* emit_load_s3 ****************************************************************
- reg = tempreg;
- } else
- reg = GET_LOW_REG(src->regoff);
+ Emits a possible load of the third source operand.
+
+*******************************************************************************/
+
+s4 emit_load_s3(jitdata *jd, instruction *iptr, s4 tempreg)
+{
+ stackptr src;
+ s4 reg;
+
+ /* get required compiler data */
+
+ src = iptr->sx.s23.s3.var;
+
+ reg = emit_load(jd, iptr, src, tempreg);
return reg;
}
-/* emit_load_s2_low ************************************************************
+/* emit_load_s1_low ************************************************************
- Emits a possible load of the low 32-bits of the second long source
+ Emits a possible load of the low 32-bits of the first long source
operand.
*******************************************************************************/
-s4 emit_load_s2_low(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
+s4 emit_load_s1_low(jitdata *jd, instruction *iptr, s4 tempreg)
{
- codegendata *cd;
- s4 disp;
+ stackptr src;
s4 reg;
- assert(src->type == TYPE_LNG);
/* get required compiler data */
- cd = jd->cd;
+ src = iptr->s1.var;
- if (src->flags & INMEMORY) {
- COUNT_SPILLS;
+ reg = emit_load_low(jd, iptr, src, tempreg);
- disp = src->regoff * 4;
+ return reg;
+}
- M_ILD(tempreg, REG_SP, disp);
- reg = tempreg;
- } else
- reg = GET_LOW_REG(src->regoff);
+
+
+/* emit_load_s2_low ************************************************************
+
+ Emits a possible load of the low 32-bits of the second long source
+ operand.
+
+*******************************************************************************/
+
+s4 emit_load_s2_low(jitdata *jd, instruction *iptr, s4 tempreg)
+{
+ stackptr src;
+ s4 reg;
+
+ /* get required compiler data */
+
+ src = iptr->sx.s23.s2.var;
+
+ reg = emit_load_low(jd, iptr, src, tempreg);
return reg;
}
*******************************************************************************/
-s4 emit_load_s1_high(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
+s4 emit_load_s1_high(jitdata *jd, instruction *iptr, s4 tempreg)
{
- codegendata *cd;
- s4 disp;
+ stackptr src;
s4 reg;
- assert(src->type == TYPE_LNG);
-
/* get required compiler data */
- cd = jd->cd;
-
- if (src->flags & INMEMORY) {
- COUNT_SPILLS;
-
- disp = src->regoff * 4;
-
- M_ILD(tempreg, REG_SP, disp + 4);
+ src = iptr->s1.var;
- reg = tempreg;
- } else
- reg = GET_HIGH_REG(src->regoff);
+ reg = emit_load_high(jd, iptr, src, tempreg);
return reg;
}
*******************************************************************************/
-s4 emit_load_s2_high(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
+s4 emit_load_s2_high(jitdata *jd, instruction *iptr, s4 tempreg)
{
- codegendata *cd;
- s4 disp;
+ stackptr src;
s4 reg;
- assert(src->type == TYPE_LNG);
-
/* get required compiler data */
- cd = jd->cd;
-
- if (src->flags & INMEMORY) {
- COUNT_SPILLS;
-
- disp = src->regoff * 4;
+ src = iptr->sx.s23.s2.var;
- M_ILD(tempreg, REG_SP, disp + 4);
-
- reg = tempreg;
- } else
- reg = GET_HIGH_REG(src->regoff);
+ reg = emit_load_high(jd, iptr, src, tempreg);
return reg;
}
*******************************************************************************/
-void emit_store(jitdata *jd, instruction *iptr, stackptr dst, s4 d)
+inline void emit_store(jitdata *jd, instruction *iptr, stackptr dst, s4 d)
{
codegendata *cd;
cd = jd->cd;
- if (dst->flags & INMEMORY) {
+ if (IS_INMEMORY(dst->flags)) {
COUNT_SPILLS;
if (IS_FLT_DBL_TYPE(dst->type)) {
M_DST(d, REG_SP, dst->regoff * 4);
else
M_FST(d, REG_SP, dst->regoff * 4);
-
- } else {
+ }
+ else {
if (IS_2_WORD_TYPE(dst->type))
M_LST(d, REG_SP, dst->regoff * 4);
else
*******************************************************************************/
-void emit_store_low(jitdata *jd, instruction *iptr, stackptr dst, s4 d)
+inline void emit_store_low(jitdata *jd, instruction *iptr, stackptr dst, s4 d)
{
codegendata *cd;
cd = jd->cd;
- if (dst->flags & INMEMORY) {
+ if (IS_INMEMORY(dst->flags)) {
COUNT_SPILLS;
M_IST(GET_LOW_REG(d), REG_SP, dst->regoff * 4);
}
*******************************************************************************/
-void emit_store_high(jitdata *jd, instruction *iptr, stackptr dst, s4 d)
+inline void emit_store_high(jitdata *jd, instruction *iptr, stackptr dst, s4 d)
{
codegendata *cd;
cd = jd->cd;
- if (dst->flags & INMEMORY) {
+ if (IS_INMEMORY(dst->flags)) {
COUNT_SPILLS;
M_IST(GET_HIGH_REG(d), REG_SP, dst->regoff * 4 + 4);
}
}
+/* emit_store_dst **************************************************************
+
+ This function generates the code to store the result of an
+ operation back into a spilled pseudo-variable. If the
+ pseudo-variable has not been spilled in the first place, this
+ function will generate nothing.
+
+*******************************************************************************/
+
+void emit_store_dst(jitdata *jd, instruction *iptr, s4 d)
+{
+ stackptr dst;
+
+ dst = iptr->dst.var;
+
+ emit_store(jd, iptr, dst, d);
+}
+
/* emit_copy *******************************************************************
- XXX
+ Generates a register/memory to register/memory copy.
*******************************************************************************/
if ((src->regoff != dst->regoff) ||
((src->flags ^ dst->flags) & INMEMORY)) {
- if (IS_LNG_TYPE(src->type))
- d = codegen_reg_of_var(rd, iptr->opc, dst, REG_ITMP12_PACKED);
- else
- d = codegen_reg_of_var(rd, iptr->opc, dst, REG_ITMP1);
- s1 = emit_load_s1(jd, iptr, src, d);
+ /* If one of the variables resides in memory, we can eliminate
+ the register move from/to the temporary register with the
+ order of getting the destination register and the load. */
+
+ if (IS_INMEMORY(src->flags)) {
+ if (IS_LNG_TYPE(src->type))
+ d = codegen_reg_of_var(rd, iptr->opc, dst, REG_ITMP12_PACKED);
+ else
+ d = codegen_reg_of_var(rd, iptr->opc, dst, REG_ITMP1);
+
+ s1 = emit_load(jd, iptr, src, d);
+ }
+ else {
+ if (IS_LNG_TYPE(src->type))
+ s1 = emit_load(jd, iptr, src, REG_ITMP12_PACKED);
+ else
+ s1 = emit_load(jd, iptr, src, REG_ITMP1);
+
+ d = codegen_reg_of_var(rd, iptr->opc, dst, s1);
+ }
if (s1 != d) {
if (IS_FLT_DBL_TYPE(src->type)) {
}
-void emit_ifcc_iconst(codegendata *cd, s4 if_op, stackptr src, instruction *iptr)
+/* emit_exception_stubs ********************************************************
+
+ Generates the code for the exception stubs.
+
+*******************************************************************************/
+
+void emit_exception_stubs(jitdata *jd)
{
- if (iptr->dst->flags & INMEMORY) {
- s4 offset = 0;
+ codegendata *cd;
+ registerdata *rd;
+ exceptionref *eref;
+ s4 targetdisp;
- if (src->flags & INMEMORY) {
- emit_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4);
+ /* get required compiler data */
- } else {
- emit_test_reg_reg(cd, src->regoff, src->regoff);
- }
+ cd = jd->cd;
+ rd = jd->rd;
- offset += 7;
- CALCOFFSETBYTES(offset, REG_SP, iptr->dst->regoff * 4);
-
- emit_jcc(cd, if_op, offset + (iptr[1].opc == ICMD_ELSE_ICONST) ? 5 + offset : 0);
- emit_mov_imm_membase(cd, iptr->val.i, REG_SP, iptr->dst->regoff * 4);
+ /* generate exception stubs */
- if (iptr[1].opc == ICMD_ELSE_ICONST) {
- emit_jmp_imm(cd, offset);
- emit_mov_imm_membase(cd, iptr[1].val.i, REG_SP, iptr->dst->regoff * 4);
+ targetdisp = 0;
+
+ for (eref = cd->exceptionrefs; eref != NULL; eref = eref->next) {
+ gen_resolvebranch(cd->mcodebase + eref->branchpos,
+ eref->branchpos,
+ cd->mcodeptr - cd->mcodebase);
+
+ MCODECHECK(512);
+
+ /* Check if the exception is an
+ ArrayIndexOutOfBoundsException. If so, move index register
+ into REG_ITMP1. */
+
+ if (eref->reg != -1)
+ M_INTMOVE(eref->reg, REG_ITMP1);
+
+ /* calcuate exception address */
+
+ M_MOV_IMM(0, REG_ITMP2_XPC);
+ dseg_adddata(cd);
+ M_AADD_IMM32(eref->branchpos - 6, REG_ITMP2_XPC);
+
+ /* move function to call into REG_ITMP3 */
+
+ M_MOV_IMM(eref->function, REG_ITMP3);
+
+ if (targetdisp == 0) {
+ targetdisp = cd->mcodeptr - cd->mcodebase;
+
+ M_ASUB_IMM(5 * 4, REG_SP);
+
+ /* first store REG_ITMP1 so we can use it */
+
+ M_AST(REG_ITMP1, REG_SP, 4 * 4); /* for AIOOBE */
+
+ M_AST_IMM(0, REG_SP, 0 * 4);
+ dseg_adddata(cd);
+ M_MOV(REG_SP, REG_ITMP1);
+ M_AADD_IMM(5 * 4, REG_ITMP1);
+ M_AST(REG_ITMP1, REG_SP, 1 * 4);
+ M_ALD(REG_ITMP1, REG_SP, (5 + cd->stackframesize) * 4);
+ M_AST(REG_ITMP1, REG_SP, 2 * 4);
+ M_AST(REG_ITMP2_XPC, REG_SP, 3 * 4);
+
+ M_CALL(REG_ITMP3);
+
+ M_ALD(REG_ITMP2_XPC, REG_SP, 3 * 4);
+ M_AADD_IMM(5 * 4, REG_SP);
+
+ M_MOV_IMM(asm_handle_exception, REG_ITMP3);
+ M_JMP(REG_ITMP3);
+ }
+ else {
+ M_JMP_IMM((cd->mcodebase + targetdisp) -
+ (cd->mcodeptr + PATCHER_CALL_SIZE));
}
+ }
+}
- } else {
- if (src->flags & INMEMORY) {
- emit_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4);
- } else {
- emit_test_reg_reg(cd, src->regoff, src->regoff);
+/* emit_patcher_stubs **********************************************************
+
+ Generates the code for the patcher stubs.
+
+*******************************************************************************/
+
+void emit_patcher_stubs(jitdata *jd)
+{
+ codegendata *cd;
+ patchref *pref;
+ u8 mcode;
+ u1 *savedmcodeptr;
+ u1 *tmpmcodeptr;
+ s4 targetdisp;
+ s4 disp;
+
+ /* get required compiler data */
+
+ cd = jd->cd;
+
+ /* generate code patching stub call code */
+
+ targetdisp = 0;
+
+ for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
+ /* check code segment size */
+
+ MCODECHECK(512);
+
+ /* Get machine code which is patched back in later. A
+ `call rel32' is 5 bytes long. */
+
+ savedmcodeptr = cd->mcodebase + pref->branchpos;
+ mcode = *((u8 *) savedmcodeptr);
+
+ /* patch in `call rel32' to call the following code */
+
+ tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */
+ cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */
+
+ M_CALL_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE));
+
+ cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
+
+ /* save REG_ITMP3 */
+
+ M_PUSH(REG_ITMP3);
+
+ /* move pointer to java_objectheader onto stack */
+
+#if defined(ENABLE_THREADS)
+ (void) dseg_addaddress(cd, NULL); /* flcword */
+ (void) dseg_addaddress(cd, lock_get_initial_lock_word());
+ disp = dseg_addaddress(cd, NULL); /* vftbl */
+
+ M_MOV_IMM(0, REG_ITMP3);
+ dseg_adddata(cd);
+ M_AADD_IMM(disp, REG_ITMP3);
+ M_PUSH(REG_ITMP3);
+#else
+ M_PUSH_IMM(0);
+#endif
+
+ /* move machine code bytes and classinfo pointer into registers */
+
+ M_PUSH_IMM(mcode >> 32);
+ M_PUSH_IMM(mcode);
+ M_PUSH_IMM(pref->ref);
+ M_PUSH_IMM(pref->patcher);
+
+ if (targetdisp == 0) {
+ targetdisp = cd->mcodeptr - cd->mcodebase;
+
+ M_MOV_IMM(asm_patcher_wrapper, REG_ITMP3);
+ M_JMP(REG_ITMP3);
+ }
+ else {
+ M_JMP_IMM((cd->mcodebase + targetdisp) -
+ (cd->mcodeptr + PATCHER_CALL_SIZE));
}
+ }
+}
+
+
+/* emit_replacement_stubs ******************************************************
- emit_jcc(cd, if_op, (iptr[1].opc == ICMD_ELSE_ICONST) ? 10 : 5);
- emit_mov_imm_reg(cd, iptr->val.i, iptr->dst->regoff);
+ Generates the code for the replacement stubs.
- if (iptr[1].opc == ICMD_ELSE_ICONST) {
- emit_jmp_imm(cd, 5);
- emit_mov_imm_reg(cd, iptr[1].val.i, iptr->dst->regoff);
+*******************************************************************************/
+
+void emit_replacement_stubs(jitdata *jd)
+{
+ codegendata *cd;
+ codeinfo *code;
+ rplpoint *rplp;
+ s4 disp;
+ s4 i;
+
+ /* get required compiler data */
+
+ cd = jd->cd;
+ code = jd->code;
+
+ rplp = code->rplpoints;
+
+ for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
+ /* check code segment size */
+
+ MCODECHECK(512);
+
+ /* note start of stub code */
+
+ rplp->outcode = (u1 *) (ptrint) (cd->mcodeptr - cd->mcodebase);
+
+ /* make machine code for patching */
+
+ disp = (ptrint) (rplp->outcode - rplp->pc) - 5;
+
+ rplp->mcode = 0xe9 | ((u8) disp << 8);
+
+ /* push address of `rplpoint` struct */
+
+ M_PUSH_IMM(rplp);
+
+ /* jump to replacement function */
+
+ M_PUSH_IMM(asm_replacement_out);
+ M_RET;
+ }
+}
+
+
+/* emit_verbosecall_enter ******************************************************
+
+ Generates the code for the call trace.
+
+*******************************************************************************/
+
+#if !defined(NDEBUG)
+void emit_verbosecall_enter(jitdata *jd)
+{
+ methodinfo *m;
+ codegendata *cd;
+ registerdata *rd;
+ methoddesc *md;
+ s4 disp;
+ s4 i, t;
+
+ /* get required compiler data */
+
+ m = jd->m;
+ cd = jd->cd;
+ rd = jd->rd;
+
+ md = m->parseddesc;
+
+ /* mark trace code */
+
+ M_NOP;
+
+ /* methodinfo* + arguments + return address */
+
+ disp = TRACE_ARGS_NUM * 8 + 4 + INT_TMP_CNT * 4 +
+ cd->stackframesize * 4 + 4;
+
+ M_ASUB_IMM(TRACE_ARGS_NUM * 8 + 4 + INT_TMP_CNT * 4, REG_SP);
+
+ /* save temporary registers for leaf methods */
+
+ for (i = 0; i < INT_TMP_CNT; i++)
+ M_IST(rd->tmpintregs[i], REG_SP, TRACE_ARGS_NUM * 8 + 4 + i * 4);
+
+ for (i = 0; i < md->paramcount && i < TRACE_ARGS_NUM; i++) {
+ t = md->paramtypes[i].type;
+
+ if (IS_INT_LNG_TYPE(t)) {
+ if (IS_2_WORD_TYPE(t)) {
+ M_LLD(REG_ITMP12_PACKED, REG_SP, disp);
+ M_LST(REG_ITMP12_PACKED, REG_SP, i * 8);
+ }
+ else if (IS_ADR_TYPE(t)) {
+ M_ALD(REG_ITMP1, REG_SP, disp);
+ M_AST(REG_ITMP1, REG_SP, i * 8);
+ M_IST_IMM(0, REG_SP, i * 8 + 4);
+ }
+ else {
+ M_ILD(EAX, REG_SP, disp);
+ emit_cltd(cd);
+ M_LST(EAX_EDX_PACKED, REG_SP, i * 8);
+ }
+ }
+ else {
+ if (IS_2_WORD_TYPE(t)) {
+ M_DLD(REG_NULL, REG_SP, disp);
+ M_DST(REG_NULL, REG_SP, i * 8);
+ }
+ else {
+ M_FLD(REG_NULL, REG_SP, disp);
+ M_FST(REG_NULL, REG_SP, i * 8);
+ M_IST_IMM(0, REG_SP, i * 8 + 4);
+ }
}
+
+ disp += (IS_2_WORD_TYPE(t)) ? 8 : 4;
}
+
+ M_AST_IMM(m, REG_SP, TRACE_ARGS_NUM * 8);
+
+ M_MOV_IMM(builtin_trace_args, REG_ITMP1);
+ M_CALL(REG_ITMP1);
+
+ /* restore temporary registers for leaf methods */
+
+ for (i = 0; i < INT_TMP_CNT; i++)
+ M_ILD(rd->tmpintregs[i], REG_SP, TRACE_ARGS_NUM * 8 + 4 + i * 4);
+
+ M_AADD_IMM(TRACE_ARGS_NUM * 8 + 4 + INT_TMP_CNT * 4, REG_SP);
+
+ /* mark trace code */
+
+ M_NOP;
+}
+#endif /* !defined(NDEBUG) */
+
+
+/* emit_verbosecall_exit *******************************************************
+
+ Generates the code for the call trace.
+
+*******************************************************************************/
+
+#if !defined(NDEBUG)
+void emit_verbosecall_exit(jitdata *jd)
+{
+ methodinfo *m;
+ codegendata *cd;
+ registerdata *rd;
+
+ /* get required compiler data */
+
+ m = jd->m;
+ cd = jd->cd;
+ rd = jd->rd;
+
+ /* mark trace code */
+
+ M_NOP;
+
+ M_ASUB_IMM(4 + 8 + 8 + 4 + 8, REG_SP); /* +8: keep stack 16-byte aligned */
+
+ M_AST_IMM(m, REG_SP, 0 * 4);
+
+ M_LST(REG_RESULT_PACKED, REG_SP, 1 * 4);
+
+ M_DSTNP(REG_NULL, REG_SP, 1 * 4 + 1 * 8);
+ M_FSTNP(REG_NULL, REG_SP, 1 * 4 + 2 * 8);
+
+ M_MOV_IMM(builtin_displaymethodstop, REG_ITMP1);
+ M_CALL(REG_ITMP1);
+
+ M_LLD(REG_RESULT_PACKED, REG_SP, 1 * 4);
+
+ M_AADD_IMM(4 + 8 + 8 + 4 + 8, REG_SP);
+
+ /* mark trace code */
+
+ M_NOP;
}
+#endif /* !defined(NDEBUG) */
/* code generation functions **************************************************/
projects / cacao.git / blobdiff